| /linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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| /linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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| D | k3-j7200.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <1>;
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| D | k3-j721e.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
39 #address-cells = <1>;
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| /linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap806-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap807-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| /linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| /linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
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| /linux-5.10/arch/powerpc/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
27 /* per-cpu object for tracking:
28 * - a "cache" kobject for the top-level directory
29 * - a list of "index" objects representing the cpu's local cache hierarchy
32 struct kobject *kobj; /* bare (not embedded) kobject for cache
37 /* "index" object: each cpu's cache directory has an index
38 * subdirectory corresponding to a cache object associated with the
44 struct cache *cache; member
48 * cache type */
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| /linux-5.10/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 7 * Copyright (C) 2011-2012 by Broadcom Corporation
28 #define cacheop(kva, size, linesize, op) \ argument
30 addu t1, kva, size ; \
34 addiu t1, t1, -1 ; \
36 9: cache op, 0(t0) ; \
80 /* ZSC L2 Cache Register Access Register Definitions */
111 * Returns: v0 = i cache size, v1 = I cache line size
112 * Description: compute the I-cache size and I-cache line size
128 * This field contains the number of sets (i.e., indices) per way of
129 * the instruction cache:
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| /linux-5.10/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
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| /linux-5.10/arch/riscv/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 if (rv_cache_ops && rv_cache_ops->get_priv_group) in cache_get_priv_group()
23 return rv_cache_ops->get_priv_group(this_leaf); in cache_get_priv_group()
33 for (index = 0; index < this_cpu_ci->num_leaves; index++) { in get_cacheinfo()
34 this_leaf = this_cpu_ci->info_list + index; in get_cacheinfo()
35 if (this_leaf->level == level && this_leaf->type == type) in get_cacheinfo()
46 return this_leaf ? this_leaf->size : 0; in get_cache_size()
53 return this_leaf ? (this_leaf->ways_of_associativity << 16 | in get_cache_geometry()
54 this_leaf->coherency_line_size) : in get_cache_geometry()
59 unsigned int level, unsigned int size, in ci_leaf_init() argument
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| /linux-5.10/arch/arm/mm/ |
| D | cache-v4wt.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wt.S
5 * Copyright (C) 1997-2002 Russell king
7 * ARMv4 write through cache operations support.
15 #include "proc-macros.S"
18 * The size of one data cache line.
23 * The number of data cache segments.
28 * The number of lines in a cache segment.
33 * This is the size at which it becomes more efficient to
34 * clean the whole cache, rather than using the individual
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| D | proc-xscale.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-xscale.S
25 #include <asm/pgtable-hwdef.h>
28 #include "proc-macros.S"
31 * This is the maximum size of an area which will be flushed. If the area
32 * is larger than this, then we flush the whole cache
37 * the cache line size of the I and D cache
42 * the size of the data cache
47 * Virtual address used to allocate the cache when flushed
56 * Without this the XScale core exhibits cache eviction problems and no one
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| /linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | mpc8641si-pre.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
8 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&mpic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
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| /linux-5.10/fs/squashfs/ |
| D | file.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Squashfs - a compressed read only filesystem for Linux
14 * compressed fragment block (tail-end packed block). The compressed size
19 * larger), the code implements an index cache that caches the mapping from
22 * The index cache allows Squashfs to handle large files (up to 1.75 TiB) while
23 * retaining a simple and space-efficient block list on disk. The cache
26 * The index cache is designed to be memory efficient, and by default uses
44 * Locate cache slot in range [offset, index] for specified inode. If
51 struct squashfs_sb_info *msblk = inode->i_sb->s_fs_info; in locate_meta_index()
52 int i; in locate_meta_index() local
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| /linux-5.10/arch/x86/kernel/cpu/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
35 short size; member
40 /* All the cache descriptor types we care about (no TLB or
41 trace cache entries) */
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
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| /linux-5.10/drivers/base/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * cacheinfo support - processor cache information via sysfs
26 #define cache_leaves(cpu) (ci_cacheinfo(cpu)->num_leaves)
27 #define per_cpu_cacheinfo(cpu) (ci_cacheinfo(cpu)->info_list)
38 return sib_leaf->fw_token == this_leaf->fw_token; in cache_leaves_are_shared()
41 /* OF properties to query for a given cache type */
50 .size_prop = "cache-size",
51 .line_size_props = { "cache-line-size",
52 "cache-block-size", },
53 .nr_sets_prop = "cache-sets",
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| /linux-5.10/lib/ |
| D | test_kasan.c | 1 // SPDX-License-Identifier: GPL-2.0-only
45 * Temporarily enable multi-shot mode and set panic_on_warn=0. in kasan_test_init()
59 * KUNIT_EXPECT_KASAN_FAIL() - Causes a test failure when the expression does
81 size_t size = 123; in kmalloc_oob_right() local
83 ptr = kmalloc(size, GFP_KERNEL); in kmalloc_oob_right()
86 KUNIT_EXPECT_KASAN_FAIL(test, ptr[size + OOB_TAG_OFF] = 'x'); in kmalloc_oob_right()
93 size_t size = 15; in kmalloc_oob_left() local
95 ptr = kmalloc(size, GFP_KERNEL); in kmalloc_oob_left()
98 KUNIT_EXPECT_KASAN_FAIL(test, *ptr = *(ptr - 1)); in kmalloc_oob_left()
105 size_t size = 4096; in kmalloc_node_oob_right() local
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| /linux-5.10/mm/ |
| D | slab_common.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/cache.h>
79 * Determine the size of a slab object
83 return s->object_size; in kmem_cache_size()
88 static int kmem_cache_sanity_check(const char *name, unsigned int size) in kmem_cache_sanity_check() argument
90 if (!name || in_interrupt() || size < sizeof(void *) || in kmem_cache_sanity_check()
91 size > KMALLOC_MAX_SIZE) { in kmem_cache_sanity_check()
93 return -EINVAL; in kmem_cache_sanity_check()
100 static inline int kmem_cache_sanity_check(const char *name, unsigned int size) in kmem_cache_sanity_check() argument
108 size_t i; in __kmem_cache_free_bulk() local
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| /linux-5.10/drivers/block/ |
| D | ps3vram.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ps3vram - Use extra PS3 video ram as block device.
8 * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
19 #include <asm/cell-regs.h>
38 #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
73 u64 size; member
84 struct ps3vram_cache cache; member
98 static char *size = "256M"; variable
99 module_param(size, charp, 0);
100 MODULE_PARM_DESC(size, "memory size");
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