Searched +full:hpd +full:- +full:reliable +full:- +full:delay +full:- +full:ms (Results 1 – 7 of 7) sorted by relevance
/linux-6.8/Documentation/devicetree/bindings/display/panel/ |
D | panel-edp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Douglas Anderson <dianders@chromium.org> 14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without 17 board, either for second-sourcing purposes or to support multiple SKUs 51 :<T1>:<T2>: :<--T10-->:<T11>:<T12>: 52 : +-----------------------+---------+---------+ 53 eDP -----------+ Black video | Src vid | Blk vid + [all …]
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/linux-6.8/drivers/gpu/drm/panel/ |
D | panel-edp.c | 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 #include <linux/delay.h> 46 * struct panel_delay - Describes delays for a simple panel. 50 * @hpd_reliable: Time for HPD to be reliable 53 * before the HPD signal is reliable. Ideally this is 0 but some panels, 57 * Presumably some old panels simply didn't have HPD hooked up and put 59 * hpd_absent. While that works, it's non-ideal. 64 * @hpd_absent: Time to wait if HPD isn't hooked up. 66 * Add this to the prepare delay if we know Hot Plug Detect isn't used. 68 * This is T3-max on eDP timing diagrams or the delay from power on [all …]
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/linux-6.8/drivers/gpu/drm/msm/hdmi/ |
D | hdmi_hpd.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/delay.h> 65 const struct hdmi_platform_config *config = hdmi->config; in enable_hpd_clocks() 66 struct device *dev = &hdmi->pdev->dev; in enable_hpd_clocks() 70 for (i = 0; i < config->hpd_clk_cnt; i++) { in enable_hpd_clocks() 71 if (config->hpd_freq && config->hpd_freq[i]) { in enable_hpd_clocks() 72 ret = clk_set_rate(hdmi->hpd_clks[i], in enable_hpd_clocks() 73 config->hpd_freq[i]); in enable_hpd_clocks() 77 config->hpd_clk_names[i], ret); in enable_hpd_clocks() 80 ret = clk_prepare_enable(hdmi->hpd_clks[i]); in enable_hpd_clocks() [all …]
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/linux-6.8/arch/arm64/boot/dts/qcom/ |
D | sdm845-cheza.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 25 stdout-path = "serial0:115200n8"; 29 compatible = "pwm-backlight"; 31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 32 power-supply = <&ppvar_sys>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&ap_edp_bklten>; 37 /* FIXED REGULATORS - parents above children */ [all …]
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/linux-6.8/drivers/gpu/drm/i915/display/ |
D | intel_dp.c | 107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 119 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp() 127 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr() 131 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 135 * rate -> channel coding. 143 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 156 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates() 157 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates() 169 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates() 173 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); in intel_dp_set_dpcd_sink_rates() [all …]
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D | intel_psr.c | 47 * Since Haswell Display controller supports Panel Self-Refresh on display 61 * The implementation uses the hardware-based PSR support which automatically 62 * enters/exits self-refresh mode. The hardware takes care of sending the 65 * changes to know when to exit self-refresh mode again. Unfortunately that 70 * issues the self-refresh re-enable code is done from a work queue, which 78 * entry/exit allows the HW to enter a low-power state even when page flipping 94 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 158 * In standby mode (as opposed to link-off) this makes no difference 172 * The rest of the bits are more self-explanatory and/or 178 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) in intel_encoder_can_psr() [all …]
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D | intel_ddi.c | 97 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level() 99 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level() 122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers() 125 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers() 128 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers() 129 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers() 134 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers() 139 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers() 141 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers() 153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_hdmi_ddi_buffers() [all …]
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