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/linux-5.10/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dhi6220-domain-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/hi6220-domain-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon Hi6220 domain controller
10 - Wei Xu <xuwei5@hisilicon.com>
19 Power Always ON domain controller --> hisilicon,hi6220-aoctrl
20 Media domain controller --> hisilicon,hi6220-mediactrl
21 Power Management domain controller --> hisilicon,hi6220-pmctrl
26 - enum:
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/linux-5.10/Documentation/devicetree/bindings/clock/
Dhi6220-clock.txt1 * Hisilicon Hi6220 Clock Controller
3 Clock control registers reside in different Hi6220 system controllers,
11 - compatible: the compatible should be one of the following strings to
14 - "hisilicon,hi6220-acpu-sctrl"
15 - "hisilicon,hi6220-aoctrl"
16 - "hisilicon,hi6220-sysctrl"
17 - "hisilicon,hi6220-mediactrl"
18 - "hisilicon,hi6220-pmctrl"
19 - "hisilicon,hi6220-stub-clk"
21 - reg: physical base address of the controller and length of memory mapped
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/linux-5.10/Documentation/devicetree/bindings/reset/
Dhisilicon,hi6220-reset.txt7 The reset controller registers are part of the system-ctl block on
8 hi6220 SoC.
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
15 - reg: should be register base and length as documented in the
17 - #reset-cells: 1, see below
21 compatible = "hisilicon,hi6220-sysctrl", "syscon";
23 #clock-cells = <1>;
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/linux-5.10/drivers/reset/hisilicon/
Dhi6220_reset.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon Hi6220 reset controller driver
6 * Copyright (c) 2015-2016 Hisilicon Limited.
19 #include <linux/reset-controller.h>
48 struct regmap *regmap = data->regmap; in hi6220_peripheral_assert()
60 struct regmap *regmap = data->regmap; in hi6220_peripheral_deassert()
77 struct regmap *regmap = data->regmap; in hi6220_media_assert()
86 struct regmap *regmap = data->regmap; in hi6220_media_deassert()
110 struct regmap *regmap = data->regmap; in hi6220_ao_assert()
129 struct regmap *regmap = data->regmap; in hi6220_ao_deassert()
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/linux-5.10/drivers/clk/hisilicon/
Dclk-hi6220.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon Hi6220 clock driver
11 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/hi6220-clock.h>
90 CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
197 CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
254 CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
285 CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
307 CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Hisilicon Hi6220 SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "hisilicon,hi6220";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
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