/linux-6.8/tools/perf/pmu-events/arch/riscv/ |
D | riscv-sbi-firmware.json | 39 "PublicDescription": "Sent IPI to other HART event", 42 "BriefDescription": "Sent IPI to other HART event" 45 "PublicDescription": "Received IPI from other HART event", 48 "BriefDescription": "Received IPI from other HART event" 51 "PublicDescription": "Sent FENCE.I request to other HART event", 54 "BriefDescription": "Sent FENCE.I request to other HART event" 57 "PublicDescription": "Received FENCE.I request from other HART event", 60 "BriefDescription": "Received FENCE.I request from other HART event" 63 "PublicDescription": "Sent SFENCE.VMA request to other HART event", 66 "BriefDescription": "Sent SFENCE.VMA request to other HART event" [all …]
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/linux-6.8/arch/riscv/kernel/ |
D | cpu.c | 26 * Returns the hart ID of the given device tree node, or -ENODEV if the node 27 * isn't an enabled and valid RISC-V hart node. 29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument 33 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid() 34 if (*hart == ~0UL) { in riscv_of_processor_hartid() 35 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid() 39 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid() 49 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument 58 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid() 59 if (*hart == ~0UL) { in riscv_early_of_processor_hartid() [all …]
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D | smpboot.c | 78 unsigned long hart; in acpi_parse_rintc() local 95 hart = processor->hart_id; in acpi_parse_rintc() 96 if (hart == INVALID_HARTID) { in acpi_parse_rintc() 101 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc() 113 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc() 131 unsigned long hart; in of_parse_and_init_cpus() local 137 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus() 141 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus() 149 cpuid, hart); in of_parse_and_init_cpus() 153 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
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D | machine_kexec.c | 107 * No more interrupts on this hart in machine_shutdown() 177 * suspended and this hart will be the new boot hart. 201 pr_notice("Will call new kernel at %08lx from hart id %lx\n", in machine_kexec() 205 /* Make sure the relocation code is visible to the hart */ in machine_kexec()
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D | sys_riscv.c | 50 * kernel might schedule a process on another hart. There is no way for 52 * thread->hart mappings), so we've defined a RISC-V specific system call to
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D | head.S | 186 /* We lack SMP support or have too many harts, so park this hart */ 244 /* Pick one hart to run the main boot sequence */ 339 * This hart didn't win the lottery, so we wait for the winning hart to
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/linux-6.8/Documentation/devicetree/bindings/iio/addac/ |
D | adi,ad74115.yaml | 70 10 - Current output with HART 71 11 - Current input, externally-powered, with HART 72 12 - Current input, loop-powered, with HART 188 adi,dac-hart-slew: 190 description: Whether to use a HART-compatible slew rate. 268 3 - Control HART CD 269 4 - Monitor HART CD 270 5 - Monitor HART EOM status 282 3 - Control HART RXD 283 4 - Monitor HART RXD [all …]
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D | adi,ad74413r.yaml | 20 The AD74413R differentiates itself from the AD74412R by being HART-compatible. 81 HART functions are not supported on AD74412R.
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/linux-6.8/drivers/irqchip/ |
D | irq-riscv-intc.c | 36 * on the local hart, these functions can only be called on the hart that 54 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi() 56 * chained handlers for the per-HART local interrupts. in riscv_intc_irq_eoi() 60 * will do unnecessary mask/unmask of per-HART local interrupts in riscv_intc_irq_eoi() 148 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init() 153 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init() 156 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init() 185 * The ACPI MADT will have one INTC for each CPU (or HART) in riscv_intc_acpi_init() 188 * for the INTC belonging to the boot CPU (or boot HART). in riscv_intc_acpi_init()
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/linux-6.8/arch/riscv/mm/ |
D | cacheflush.c | 36 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the 39 * execution resumes on each hart. 48 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm() 51 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm() 65 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm() 66 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm() 68 * messages are sent we still need to order this hart's writes in flush_icache_mm()
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D | context.c | 242 * we polluted the TLB of current HART so let's do TLB flushed in asids_init() 291 * behavior in a common case (a bunch of single-hart processes on a many-hart 294 * cache flush to be performed before execution resumes on each hart. This 296 * refers to the current hart. 308 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
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/linux-6.8/Documentation/devicetree/bindings/interrupt-controller/ |
D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC) 5 CPU core (HART in RISC-V terminology) and can be read or written by software. 7 Every interrupt is ultimately routed through a hart's HLIC before it 8 interrupts that hart. 40 definition of the hart whose CSRs control these local interrupts.
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D | sifive,plic-1.0.0.yaml | 14 external interrupts in the system to all hart contexts in the system, via 15 the external interrupt source in each hart. 17 A hart context is a privilege mode in a hardware execution thread. For example, 19 privilege modes per hart; machine mode and supervisor mode.
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/linux-6.8/Documentation/devicetree/bindings/riscv/ |
D | cpus.yaml | 18 hart: A hardware execution context, which contains all the state 61 Identifies that the hart uses the RISC-V instruction set 62 and identifies the type of the hart. 67 this hart. These values originate from the RISC-V Privileged 124 by this hart (see ./idle-states.yaml). 200 // Example 2: Spike ISA Simulator with 1 Hart
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/linux-6.8/arch/riscv/include/asm/ |
D | cpu_ops_sbi.h | 16 * struct sbi_hart_boot_data - Hart specific boot used during booting and 18 * @task_ptr: A pointer to the hart specific tp 19 * @stack_ptr: A pointer to the hart specific sp
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D | smp.h | 62 /* Secondary hart entry */ 66 * Obtains the hart ID of the currently executing task. This relies on
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D | barrier.h | 66 * task is marked as available for scheduling on a new hart. While I don't see 70 * the new hart.
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/linux-6.8/arch/csky/abiv2/ |
D | cacheflush.c | 47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred() 71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range() 75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
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/linux-6.8/Documentation/arch/riscv/ |
D | uabi.rst | 45 "isa" and "hart isa" lines in /proc/cpuinfo 50 "hart isa" line, in contrast, describes the set of extensions recognized by the 51 kernel on the particular hart being described, even if those extensions may not
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/linux-6.8/tools/testing/selftests/futex/ |
D | run.sh | 13 # Darren Hart <dvhart@linux.intel.com> 16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
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/linux-6.8/tools/arch/riscv/include/uapi/asm/ |
D | unistd.h | 29 * kernel might schedule a process on another hart. There is no way for 31 * thread->hart mappings), so we've defined a RISC-V specific system call to
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/linux-6.8/arch/riscv/include/uapi/asm/ |
D | unistd.h | 32 * kernel might schedule a process on another hart. There is no way for 34 * thread->hart mappings), so we've defined a RISC-V specific system call to
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/linux-6.8/tools/testing/selftests/futex/functional/ |
D | run.sh | 12 # Darren Hart <dvhart@linux.intel.com> 15 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
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D | futex_requeue_pi_mismatched_ops.c | 12 * Darren Hart <dvhart@linux.intel.com> 15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
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/linux-6.8/tools/testing/selftests/futex/include/ |
D | atomic.h | 11 * Darren Hart <dvhart@linux.intel.com> 14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>
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