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/linux-6.15/Documentation/devicetree/bindings/mailbox/
Dmicrochip,sbi-ipc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Inter-processor communication (IPC) mailbox controller
10 - Valentina Fernandez <valentina.fernandezalanis@microchip.com>
13 The Microchip Inter-processor Communication (IPC) facilitates
20 - description:
22 mode (s-mode). This SBI interface is compatible with the Mi-V
23 Inter-hart Communication (IHC) IP.
[all …]
/linux-6.15/arch/riscv/kernel/
Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
30 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
36 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
37 return -ENODEV; in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
[all …]
Dsmpboot.c1 // SPDX-License-Identifier: GPL-2.0-only
56 /* This covers non-smp usecase mandated by "nosmp" option */ in smp_prepare_cpus()
69 static unsigned int cpu_count = 1;
73 unsigned long hart; in acpi_parse_rintc() local
82 if (!(processor->flags & ACPI_MADT_ENABLED)) in acpi_parse_rintc()
86 return -EINVAL; in acpi_parse_rintc()
88 acpi_table_print_madt_entry(&header->common); in acpi_parse_rintc()
90 hart = processor->hart_id; in acpi_parse_rintc()
91 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
96 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
[all …]
Dmachine_kexec.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 FORTH-ICS/CARV
22 * machine_kexec_prepare - Initialize kexec
33 struct kimage_arch *internal = &image->arch; in machine_kexec_prepare()
40 for (i = 0; i < image->nr_segments; i++) { in machine_kexec_prepare()
41 if (image->segment[i].memsz <= sizeof(fdt)) in machine_kexec_prepare()
44 if (image->file_mode) in machine_kexec_prepare()
45 memcpy(&fdt, image->segment[i].buf, sizeof(fdt)); in machine_kexec_prepare()
46 else if (copy_from_user(&fdt, image->segment[i].buf, sizeof(fdt))) in machine_kexec_prepare()
52 internal->fdt_addr = (unsigned long) image->segment[i].mem; in machine_kexec_prepare()
[all …]
Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <asm/asm-offsets.h>
18 #include "efi-header.S"
23 * Image header expected by Linux boot-loaders. The image header data
32 c.li s4,-13
42 /* Image load offset (0MB) from start of RAM for M-mode */
54 .dword _end - _start
63 .word pe_head_start - _start
84 la a2, 1f
108 1:
[all …]
/linux-6.15/Documentation/devicetree/bindings/iio/addac/
Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
28 maxItems: 1
30 spi-max-frequency:
[all …]
Dadi,ad74413r.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74412R and AD74413R are quad-channel software configurable input/output
18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
27 - adi,ad74412r
28 - adi,ad74413r
31 maxItems: 1
[all …]
/linux-6.15/arch/riscv/mm/
Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
30 on_each_cpu(ipi_remote_fence_i, NULL, 1); in flush_icache_all()
35 * Performs an icache flush for the given MM context. RISC-V has no direct
39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
42 * execution resumes on each hart.
51 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
52 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
54 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
65 if (mm == current->active_mm && local) { in flush_icache_mm()
68 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
[all …]
Dcontext.c1 // SPDX-License-Identifier: GPL-2.0
87 /* Mark ASID #0 as used because it is used at boot-time */ in __flush_context()
90 /* Queue a TLB invalidation for each CPU on next context-switch */ in __flush_context()
96 static u32 cur_idx = 1; in __new_context()
97 unsigned long cntx = atomic_long_read(&mm->context.id); in __new_context()
115 * re-use it if possible. in __new_context()
136 asid = find_next_zero_bit(context_asid_map, num_asids, 1); in __new_context()
150 cntx = atomic_long_read(&mm->context.id); in set_mm_asid()
153 * If our active_context is non-zero and the context matches the in set_mm_asid()
159 * - We get a zero back from the cmpxchg and end up waiting on the in set_mm_asid()
[all …]
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
[all …]
Driscv,aplic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
[all …]
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
[all …]
/linux-6.15/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some registers. This
[all …]
/linux-6.15/drivers/irqchip/
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
48 * on the local hart, these functions can only be called on the hart that
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
[all …]
Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
[all …]
/linux-6.15/Documentation/arch/riscv/
Dcmodx.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux
9 (icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the
14 applications. At any point the scheduler may migrate a task onto a new hart. If
16 storage with fence.i, the icache on the new hart will no longer be clean. This
17 is due to the behavior of fence.i only affecting the hart that it is called on.
18 Thus, the hart that the task has been migrated to may not have synchronized
23 userspace. The syscall performs a one-off icache flushing operation. The prctl
29 when the memory map being used by a hart changes. If the prctl() context caused
35 ---------------------
[all …]
/linux-6.15/arch/csky/abiv2/
Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
24 if (test_and_set_bit(PG_dcache_clean, &folio->flags)) in update_mmu_cache_range()
33 if (vma->vm_flags & VM_EXEC) in update_mmu_cache_range()
42 cpumask_t *mask = &mm->context.icache_stale_mask; in flush_icache_deferred()
47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
64 if (mm == current->mm) { in flush_icache_mm_range()
71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
72 mask = &mm->context.icache_stale_mask; in flush_icache_mm_range()
75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
[all …]
/linux-6.15/tools/testing/selftests/futex/
Drun.sh2 # SPDX-License-Identifier: GPL-2.0-or-later
13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
23 if [ $? -eq 0 ]; then
24 USE_COLOR=1
/linux-6.15/tools/testing/selftests/futex/functional/
Drun.sh2 # SPDX-License-Identifier: GPL-2.0-or-later
12 # Darren Hart <dvhart@linux.intel.com>
15 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
16 # 2010-Jan-6: Add futex_wait_uninitialized_heap and futex_wait_private_mapped_file
22 if [ -z "$USE_COLOR" ]; then
24 if [ $? -eq 0 ]; then
25 USE_COLOR=1
29 if [ "$USE_COLOR" -eq 1 ]; then
30 COLOR="-c"
38 ./futex_requeue_pi $COLOR -b
[all …]
Dfutex_requeue_pi_mismatched_ops.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * 1. Block a thread using FUTEX_WAIT
8 * 2. Attempt to use FUTEX_CMP_REQUEUE_PI on the futex from 1.
9 * 3. The kernel must detect the mismatch and return -EINVAL.
12 * Darren Hart <dvhart@linux.intel.com>
15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
29 #define TEST_NAME "futex-requeue-pi-mismatched-ops"
38 printf(" -c Use color\n"); in usage()
39 printf(" -h Display this help message\n"); in usage()
40 printf(" -v L Verbosity level: %d=QUIET %d=CRITICAL %d=INFO\n", in usage()
[all …]
/linux-6.15/tools/testing/selftests/futex/include/
Datomic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * http://gcc.gnu.org/onlinedocs/gcc-4.1.0/gcc/Atomic-Builtins.html
11 * Darren Hart <dvhart@linux.intel.com>
14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>
28 * atomic_cmpxchg() - Atomic compare and exchange
33 * Return the old value of addr->val.
38 return __sync_val_compare_and_swap(&addr->val, oldval, newval); in atomic_cmpxchg()
42 * atomic_inc() - Atomic incrememnt
45 * Return the new value of addr->val.
50 return __sync_add_and_fetch(&addr->val, 1); in atomic_inc()
[all …]
Dlogging.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
31 #define BRIGHT '1'
34 #define RED '3', '1'
57 #define VCRITICAL 1
64 #define RET_ERROR -1
65 #define RET_FAIL -2
68 * log_color() - Use colored output for PASS, ERROR, and FAIL strings
69 * @use_color: use color (1) or not (0)
[all …]
/linux-6.15/include/linux/irqchip/
Driscv-imsic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 * XLEN-1 12 0
52 * -------------------------------------------------------------
53 * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
54 * -------------------------------------------------------------
57 /* Bits representing Guest index, HART index, and Group index */
72 /* Per-CPU IMSIC addresses */
/linux-6.15/arch/riscv/include/asm/
Dsmp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
57 /* Secondary hart entry */
61 * Obtains the hart ID of the currently executing task. This relies on
64 #define raw_smp_processor_id() (current_thread_info()->cpu)
82 return -1; in riscv_hartid_to_cpuid()

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