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/linux-6.8/Documentation/devicetree/bindings/clock/
Dgoogle,gs101-clock.yaml4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
7 title: Google GS101 SoC clock controller
13 Google GS101 clock controller is comprised of several CMU units, generating
25 'dt-bindings/clock/gs101.h' header.
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
32 - google,gs101-cmu-misc
61 - google,gs101-cmu-top
62 - google,gs101-cmu-apm
77 const: google,gs101-cmu-misc
[all …]
/linux-6.8/arch/arm64/boot/dts/exynos/google/
Dgs101.dtsi3 * GS101 SoC
9 #include <dt-bindings/clock/google,gs101.h>
15 compatible = "google,gs101";
287 compatible = "google,gs101-cmu-misc";
296 compatible = "google,gs101-wdt";
308 compatible = "google,gs101-wdt";
343 compatible = "google,gs101-peric0-sysreg", "syscon";
348 compatible = "google,gs101-pinctrl";
354 compatible = "google,gs101-usi",
367 compatible = "google,gs101-uart";
[all …]
Dgs101-oriole.dts13 #include "gs101-pinctrl.h"
14 #include "gs101.dtsi"
18 compatible = "google,gs101-oriole", "google,gs101";
Dgs101-pinctrl.h3 * Pinctrl binding constants for GS101
21 /* GS101 drive strengths */
DMakefile4 gs101-oriole.dtb \
Dgs101-pinctrl.dtsi3 * GS101 SoC pin-mux and pin-config device tree source
9 #include "gs101-pinctrl.h"
/linux-6.8/Documentation/devicetree/bindings/arm/
Dgoogle.yaml16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
22 - SoC ID ("gs101")
30 e.g. gs101 and gs101-oriole.
40 - google,gs101-oriole
41 - const: google,gs101
/linux-6.8/Documentation/devicetree/bindings/watchdog/
Dsamsung-wdt.yaml21 - google,gs101-wdt # for Google gs101
52 or Google gs101).
58 Exynos5420, Exynos7, Exynos850 and gs101).
74 - google,gs101-wdt
88 - google,gs101-wdt
/linux-6.8/Documentation/devicetree/bindings/soc/samsung/
Dsamsung,exynos-sysreg.yaml17 - google,gs101-apm-sysreg
18 - google,gs101-peric0-sysreg
19 - google,gs101-peric1-sysreg
Dexynos-pmu.yaml18 - google,gs101-pmu
39 - google,gs101-pmu
Dexynos-usi.yaml28 - google,gs101-usi
/linux-6.8/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm64.c940 /* pin banks of gs101 pin-controller (ALIVE) */
952 /* pin banks of gs101 pin-controller (FAR_ALIVE) */
960 /* pin banks of gs101 pin-controller (GSACORE) */
967 /* pin banks of gs101 pin-controller (GSACTRL) */
972 /* pin banks of gs101 pin-controller (PERIC0) */
996 /* pin banks of gs101 pin-controller (PERIC1) */
1008 /* pin banks of gs101 pin-controller (HSI1) */
1014 /* pin banks of gs101 pin-controller (HSI2) */
1023 /* pin banks of gs101 pin-controller (ALIVE) */
1030 /* pin banks of gs101 pin-controller (FAR_ALIVE) */
[all …]
Dpinctrl-samsung.c1315 { .compatible = "google,gs101-pinctrl",
/linux-6.8/Documentation/devicetree/bindings/serial/
Dsamsung_uart.yaml24 - google,gs101-uart
142 - google,gs101-uart
/linux-6.8/drivers/clk/samsung/
DMakefile24 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
Dclk-gs101.c6 * Common Clock Framework support for GS101.
14 #include <dt-bindings/clock/google,gs101.h>
1448 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
2496 .compatible = "google,gs101-cmu-apm",
2499 .compatible = "google,gs101-cmu-misc",
2507 .name = "gs101-cmu",
/linux-6.8/Documentation/devicetree/bindings/pinctrl/
Dsamsung,pinctrl-wakeup-interrupt.yaml48 - google,gs101-wakeup-eint
Dsamsung,pinctrl.yaml38 - google,gs101-pinctrl
/linux-6.8/include/dt-bindings/clock/
Dgoogle,gs101.h6 * Device Tree binding constants for Google gs101 clock controller.
/linux-6.8/drivers/watchdog/
Ds3c2410_wdt.c307 { .compatible = "google,gs101-wdt",
/linux-6.8/drivers/tty/serial/
Dsamsung_tty.c2596 .name = "gs101-uart",
2619 { .compatible = "google,gs101-uart",
/linux-6.8/
DMAINTAINERS9085 F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
9087 F: drivers/clk/samsung/clk-gs101.c
9088 F: include/dt-bindings/clock/google,gs101.h