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/linux-5.10/Documentation/devicetree/bindings/mtd/
Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI) binding
10 - Han Xu <han.xu@nxp.com>
13 - $ref: "nand-controller.yaml"
16 The GPMI nand controller provides an interface to control the NAND
17 flash chips. The device tree may optionally contain sub-nodes
24 - enum:
[all …]
/linux-5.10/drivers/mtd/nand/raw/gpmi-nand/
Dgpmi-nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
23 /* Resource names for the GPMI NAND driver. */
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
46 * SFTRST needs 3 GPMI clocks to settle, the reference manual in clear_poll_bit()
[all …]
Dgpmi-nand.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
26 * struct bch_geometry - BCH geometry description.
41 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
43 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
61 * struct boot_rom_geometry - Boot ROM geometry description.
88 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
132 /* NAND Boot issue */
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi_nand.o
3 gpmi_nand-objs += gpmi-nand.o
Dbch-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Freescale GPMI NAND Flash Driver
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mm-ddr4-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include "imx8mm-evk.dtsi"
12 compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";
15 pinctrl-0 = <&pinctrl_gpio_led_2>;
23 &gpmi {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpmi_nand>;
26 nand-on-flash-bbt;
31 pinctrl_gpmi_nand: gpmi-nand {
Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mn-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
[all …]
/linux-5.10/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "NAND ECC Smart Media byte order"
14 tristate "Raw/Parallel NAND Device Support"
20 NAND flash devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
45 Enable the driver for NAND flash on Intel Moorestown, using the
46 Denali NAND controller core.
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_MTD_RAW_NAND) += nand.o
4 obj-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += nand_ecc.o
5 nand-$(CONFIG_MTD_NAND_ECC_SW_BCH) += nand_bch.o
6 obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o
8 obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o
9 obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
10 obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
11 obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o
12 obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
[all …]
/linux-5.10/arch/arm/boot/dts/
Dimx6ull-phytec-segin-lc-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6ull-phytec-phycore-som.dtsi"
10 #include "imx6ull-phytec-segin.dtsi"
11 #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
14 model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
15 compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
16 "phytec,imx6ull-pcl063", "fsl,imx6ull";
31 &gpmi {
Dimx6dl-phytec-mira-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6qdl-phytec-phycore-som.dtsi"
10 #include "imx6qdl-phytec-mira.dtsi"
13 model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
14 compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06",
15 "phytec,imx6qdl-pcm058", "fsl,imx6dl";
18 stdout-path = &uart2;
23 max-speed = <100>;
30 &gpmi {
Dimx6qp-phytec-mira-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
7 /dts-v1/;
9 #include "imx6qdl-phytec-phycore-som.dtsi"
10 #include "imx6qdl-phytec-mira.dtsi"
13 model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
14 compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
15 "phytec,imx6qdl-pcm058", "fsl,imx6qp";
18 stdout-path = &uart2;
30 &gpmi {
Dimx6q-phytec-mira-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6qdl-phytec-phycore-som.dtsi"
10 #include "imx6qdl-phytec-mira.dtsi"
13 model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
14 compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
15 "phytec,imx6qdl-pcm058", "fsl,imx6q";
18 stdout-path = &uart2;
30 &gpmi {
Dimx6ull-phytec-segin-ff-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6ull-phytec-phycore-som.dtsi"
10 #include "imx6ull-phytec-segin.dtsi"
11 #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
14 model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
15 compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
16 "phytec,imx6ull-pcl063", "fsl,imx6ull";
51 &gpmi {
Dimx6ul-phytec-segin-ff-rdk-nand.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "imx6ul-phytec-phycore-som.dtsi"
10 #include "imx6ul-phytec-segin.dtsi"
11 #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
14 model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
15 compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
16 "phytec,imx6ul-pcl063", "fsl,imx6ul";
51 &gpmi {
Dimx6ul-isiot-nand.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
7 /dts-v1/;
9 #include "imx6ul-isiot.dtsi"
12 model = "Engicam Is.IoT MX6UL NAND Starter kit";
13 compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
16 &gpmi {
Dimx6ull-myir-mys-6ulx-eval.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "imx6ull-myir-mys-6ulx.dtsi"
12 model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
13 compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
16 &gpmi {
Dimx23.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx23-pinfunc.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&icoll>;
14 * pre-existing /chosen node to be available to insert the
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,arm926ej-s";
42 compatible = "simple-bus";
[all …]
Dimx6q-arm2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "fsl,imx6q-arm2", "fsl,imx6q";
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <0>;
26 compatible = "regulator-fixed";
28 regulator-name = "3P3V";
29 regulator-min-microvolt = <3300000>;
[all …]
Dimx28-eukrea-mbmx283lc.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
11 /dts-v1/;
12 #include "imx28-eukrea-mbmx28lc.dtsi"
24 &gpmi {
25 pinctrl-names = "default";
26 pinctrl-0 = <&gpmi_pins_a>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&i2c0_pins_a>;
43 phy-mode = "rmii";
[all …]
Dimx6ull-colibri.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
15 compatible = "pwm-backlight";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_bl_on>;
18 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
22 reg_module_3v3: regulator-module-3v3 {
23 compatible = "regulator-fixed";
24 regulator-always-on;
25 regulator-name = "+V3.3";
26 regulator-min-microvolt = <3300000>;
[all …]
Dimx28-m28cu3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
20 nand-controller@8000c000 {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
28 label = "gpmi-nfc-0-boot";
30 read-only;
34 label = "gpmi-nfc-general-use";
[all …]
Dimx28.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include "imx28-pinfunc.h"
9 #address-cells = <1>;
10 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
15 * pre-existing /chosen node to be available to insert the
42 #address-cells = <1>;
43 #size-cells = <0>;
46 compatible = "arm,arm926ej-s";
[all …]
Dimx6ul-phytec-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
12 model = "PHYTEC phyCORE-i.MX6 UltraLite";
13 compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
16 stdout-path = &uart1;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpioleds_som>;
31 compatible = "gpio-leds";
[all …]
Dimx6-logicpd-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
10 stdout-path = &uart1;
18 reg_wl18xx_vmmc: regulator-wl18xx {
19 compatible = "regulator-fixed";
20 regulator-name = "vwl1837";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
24 startup-delay-us = <70000>;
[all …]

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