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/qemu/include/hw/
H A Dqdev-core.h264 * @gpios: QLIST of named GPIOs the device provides.
266 NamedGPIOListHead gpios; member
616 * the total number of anonymous input GPIOs the device has); this
641 * be at least 0 and less than the total number of input GPIOs in that
660 * less than the total number of anonymous output GPIOs the device has
668 * qemu_irqs at once, or to connect multiple outbound GPIOs to the
694 * be at least 0 and less than the total number of output GPIOs in that
702 * qemu_irqs at once, or to connect multiple outbound GPIOs to the
758 * @dev: Device to create input GPIOs for
765 * anonymous and named GPIO lines. Stylistically, named GPIOs are
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/qemu/hw/core/
H A Dgpio.c30 QLIST_FOREACH(ngl, &dev->gpios, node) { in qdev_get_named_gpio_list()
39 QLIST_INSERT_HEAD(&dev->gpios, ngl, node); in qdev_get_named_gpio_list()
196 QLIST_INSERT_HEAD(&container->gpios, ngl, node); in qdev_pass_gpios()
H A Dqdev.c649 QLIST_INIT(&dev->gpios); in device_initfn()
672 QLIST_FOREACH_SAFE(ngl, &dev->gpios, node, next) { in device_finalize()
/qemu/docs/system/arm/
H A Dhighbank.rst15 - PL061 GPIOs
H A Db-l475e-iot01a.rst21 - STM32L4x5 GPIOs (General-purpose I/Os)
/qemu/include/hw/gpio/
H A Dstm32l4x5_gpio.h56 * anonymous input GPIOs lines under certain conditions.
H A Daspeed_gpio.h91 qemu_irq gpios[ASPEED_GPIO_MAX_NR_SETS][ASPEED_GPIOS_PER_SET]; member
/qemu/hw/gpio/
H A Dtrace-events22 pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-15 [%s]"
H A Daspeed_gpio.c32 * For each set of gpios there are three sensitivity registers that control
168 /* AST2600 only - 1.8V gpios */
170 * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the
171 * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios
339 qemu_set_irq(s->gpios[set][gpio], !!(new & mask)); in aspeed_gpio_update()
1399 /* Individual GPIOs */ in aspeed_gpio_realize()
1407 sysbus_init_irq(sbd, &s->gpios[i][j]); in aspeed_gpio_realize()
H A Dnpcm7xx_gpio.c126 /* If any pins changed state, update the outgoing GPIOs. */ in npcm7xx_gpio_update_pins()
/qemu/hw/arm/
H A Db-l475e-iot01a.c41 * GPIOs as the IM120417002 colors shield doesn't actually use
H A Dfsl-imx6ul.c68 * GPIOs in fsl_imx6ul_init()
277 * GPIOs in fsl_imx6ul_realize()
H A Dfsl-imx7.c56 * GPIOs in fsl_imx7_init()
262 * GPIOs in fsl_imx7_realize()
H A Dfsl-imx31.c163 /* Initialize all GPIOs */ in fsl_imx31_realize()
H A Dnrf51_soc.c148 /* Pass all GPIOs to the SOC layer so they are available to the board */ in nrf51_soc_realize()
H A Dfsl-imx25.c210 /* Initialize all GPIOs */ in fsl_imx25_realize()
H A Dfsl-imx6.c254 /* Initialize all GPIOs */ in fsl_imx6_realize()
/qemu/hw/misc/macio/
H A Dgpio.c69 * For now, we hard wire known GPIOs in macio_set_gpio()
H A Dmacio.c307 /* GPIOs */ in macio_newworld_realize()
/qemu/system/
H A Dqtest.c388 qtest_send(chr, "FAIL Interception of named in-GPIOs not yet supported\n"); in qtest_process_command()
401 QLIST_FOREACH(ngl, &dev->gpios, node) { in qtest_process_command()
402 /* We don't support inbound interception of named GPIOs yet */ in qtest_process_command()
/qemu/hw/misc/
H A Dxlnx-zynqmp-apu-ctrl.c61 /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */ in zynqmp_apu_pwrctl_post_write()
/qemu/tests/qtest/
H A Dstm32l4x5_syscfg-test.c29 /* SoC forwards GPIOs to SysCfg */
/qemu/hw/intc/
H A Daspeed_vic.c246 * IRQ bits, as only the top four IRQs (GPIOs) can change their event in aspeed_vic_write()
/qemu/hw/riscv/
H A Dsifive_e.c250 /* Pass all GPIOs to the SOC layer so they are available to the board */ in sifive_e_soc_realize()
H A Dsifive_u.c311 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); in create_fdt()
870 /* Pass all GPIOs to the SOC layer so they are available to the board */ in sifive_u_soc_realize()

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