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/linux/include/linux/
H A Dcompiler_attributes.h24 …* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-alias-function-a…
29 …* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-aligned-function…
30 …* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Type-Attributes.html#index-aligned-type-attribu…
31 …* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-aligned-variable…
38 * available and includes other attributes. For GCC < 9.1, __alloc_size__ gets undefined
39 * in compiler-gcc.h, due to misbehaviors.
41 …* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-alloc_005fsize-f…
48 * which seems to be required by gcc to apply the attribute according
52 …* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-always_005finlin…
67 …* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-assume_005falign…
[all …]
/linux/Documentation/translations/zh_CN/kbuild/
H A Dgcc-plugins.rst5 :Original: Documentation/kbuild/gcc-plugins.rst
9 GCC 插件基础设施
16 GCC 插件是为编译器提供额外功能的可加载模块 [1]_。它们对于运行时插装和静态分析非常有用。
21 内核的 GCC 插件基础设施支持构建树外模块、交叉编译和在单独的目录中构建。插件源文件必须由
24 目前 GCC 插件基础设施只支持一些架构。搜索 "select HAVE_GCC_PLUGINS" 来查找支持
25 GCC 插件的架构。
31 .. [1] https://gcc.gnu.org/onlinedocs/gccint/Plugins.html
32 .. [2] https://gcc.gnu.org/onlinedocs/gccint/Plugin-API.html#Plugin-API
33 .. [3] https://gcc.gnu.org/onlinedocs/gccint/GIMPLE.html
34 .. [4] https://gcc.gnu.org/onlinedocs/gccint/IPA.html
[all …]
/linux/Documentation/kbuild/
H A Dgcc-plugins.rst2 GCC plugin infrastructure
9 GCC plugins are loadable modules that provide extra features to the
14 The GCC plugin infrastructure of the kernel supports building out-of-tree
18 Currently the GCC plugin infrastructure supports only some architectures.
20 GCC plugins.
26 .. [1] https://gcc.gnu.org/onlinedocs/gccint/Plugins.html
27 .. [2] https://gcc.gnu.org/onlinedocs/gccint/Plugin-API.html#Plugin-API
28 .. [3] https://gcc.gnu.org/onlinedocs/gccint/GIMPLE.html
29 .. [4] https://gcc.gnu.org/onlinedocs/gccint/IPA.html
30 .. [5] https://gcc.gnu.org/onlinedocs/gccint/RTL.html
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574.dtsi11 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
14 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
246 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
247 <&gcc GCC_PCIE0_AHB_CLK>,
248 <&gcc GCC_PCIE0_PIPE_CLK>;
251 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
254 resets = <&gcc GCC_PCIE0_PHY_BCR>,
255 <&gcc GCC_PCIE0PHY_PHY_BCR>;
269 clocks = <&gcc GCC_PCIE2_AUX_CLK>,
270 <&gcc GCC_PCIE2_AHB_CLK>,
[all …]
H A Dipq5424.dtsi12 #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
13 #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
237 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
238 <&gcc GCC_PCIE0_AHB_CLK>,
239 <&gcc GCC_PCIE0_PIPE_CLK>;
244 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
247 resets = <&gcc GCC_PCIE0_PHY_BCR>,
248 <&gcc GCC_PCIE0PHY_PHY_BCR>;
263 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
264 <&gcc GCC_PCIE1_AHB_CLK>,
[all …]
H A Dipq8074.dtsi7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
130 clocks = <&gcc GCC_USB1_AUX_CLK>,
132 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
133 <&gcc GCC_USB1_PIPE_CLK>;
142 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB3PHY_1_PHY_BCR>;
155 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
159 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
167 clocks = <&gcc GCC_USB0_AUX_CLK>,
169 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
[all …]
H A Dipq5332.dtsi9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
161 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
163 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
225 clocks = <&gcc GCC_PRNG_AHB_CLK>;
259 clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
260 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
262 resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
263 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
264 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
279 clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
[all …]
H A Dipq5018.dtsi9 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
12 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
173 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
175 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
186 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
188 resets = <&gcc GCC_PCIE1_PHY_BCR>,
189 <&gcc GCC_PCIE1PHY_PHY_BCR>;
203 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
205 resets = <&gcc GCC_PCIE0_PHY_BCR>,
206 <&gcc GCC_PCIE0PHY_PHY_BCR>;
[all …]
H A Dipq6018.dtsi9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
238 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
242 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
250 clocks = <&gcc GCC_USB0_AUX_CLK>,
252 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
253 <&gcc GCC_USB0_PIPE_CLK>;
262 resets = <&gcc GCC_USB0_PHY_BCR>,
263 <&gcc GCC_USB3PHY_0_PHY_BCR>;
275 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
[all …]
H A Dmsm8939.dtsi8 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
13 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
234 clocks = <&gcc GCC_CRYPTO_CLK>,
235 <&gcc GCC_CRYPTO_AXI_CLK>,
236 <&gcc GCC_CRYPTO_AHB_CLK>;
489 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1201 gcc: clock-controller@1800000 { label
1202 compatible = "qcom,gcc-msm8939";
1243 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1244 <&gcc GCC_MDSS_AXI_CLK>,
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019.dtsi8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
67 clocks = <&gcc GCC_APPS_CLK_SRC>;
80 clocks = <&gcc GCC_APPS_CLK_SRC>;
93 clocks = <&gcc GCC_APPS_CLK_SRC>;
184 gcc: clock-controller@1800000 { label
185 compatible = "qcom,gcc-ipq4019";
196 clocks = <&gcc GCC_PRNG_AHB_CLK>;
229 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
230 <&gcc GCC_SDCC1_APPS_CLK>,
[all …]
H A Dqcom-ipq8064.dtsi7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
360 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
499 gcc: clock-controller@900000 { label
500 compatible = "qcom,gcc-ipq8064", "syscon";
557 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
559 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
567 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
581 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
602 clocks = <&gcc USB30_0_MASTER_CLK>;
[all …]
H A Dqcom-msm8660.dtsi6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
22 enable-method = "qcom,gcc-msm8660";
30 enable-method = "qcom,gcc-msm8660";
113 gcc: clock-controller@900000 { label
114 compatible = "qcom,gcc-msm8660";
126 clocks = <&gcc GSBI1_H_CLK>;
140 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
152 clocks = <&gcc GSBI3_H_CLK>;
165 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
177 clocks = <&gcc GSBI6_H_CLK>;
[all …]
H A Dqcom-mdm9615.dtsi12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
102 gcc: clock-controller@900000 { label
103 compatible = "qcom,gcc-mdm9615";
117 <&gcc PLL4_VOTE>,
133 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
140 clocks = <&gcc PRNG_CLK>;
142 assigned-clocks = <&gcc PRNG_CLK>;
150 clocks = <&gcc GSBI2_H_CLK>;
164 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
[all …]
H A Dqcom-msm8960.dtsi5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
301 gcc: clock-controller@900000 { label
302 compatible = "qcom,gcc-msm8960", "syscon";
348 compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
350 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
358 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
377 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
400 <&gcc PLL3>,
401 <&gcc PLL8_VOTE>,
[all …]
H A Dqcom-sdx55.dtsi9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
196 gcc: clock-controller@100000 { label
197 compatible = "qcom,gcc-sdx55";
210 clocks = <&gcc 30>,
211 <&gcc 9>;
226 resets = <&gcc GCC_QUSB2PHY_BCR>;
233 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
234 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
235 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
236 <&gcc GCC_USB3_PHY_PIPE_CLK>;
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dqcom,msm8953-camss.yaml213 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
245 clocks = <&gcc GCC_CAMSS_AHB_CLK>,
246 <&gcc GCC_CAMSS_CSI0_CLK>,
247 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
248 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
249 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
250 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
251 <&gcc GCC_CAMSS_CSI1_CLK>,
252 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
253 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
[all …]
H A Dqcom,msm8939-camss.yaml140 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
169 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
170 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
171 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
172 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
173 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
174 <&gcc GCC_CAMSS_CSI0_CLK>,
175 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
176 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
177 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
[all …]
H A Dqcom,msm8916-camss.yaml163 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
168 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
169 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
170 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
171 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
172 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
173 <&gcc GCC_CAMSS_CSI0_CLK>,
174 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
175 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
176 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,kpss-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
21 - qcom,kpss-gcc-ipq8064
22 - qcom,kpss-gcc-apq8064
23 - qcom,kpss-gcc-msm8974
24 - qcom,kpss-gcc-msm8960
25 - qcom,kpss-gcc-msm8660
26 - qcom,kpss-gcc-mdm9615
[all …]
H A Dqcom,gcc-msm8974.yaml4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
19 include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
20 include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
22 $ref: qcom,gcc.yaml#
27 - qcom,gcc-msm8226
28 - qcom,gcc-msm8974
29 - qcom,gcc-msm8974pro
30 - qcom,gcc-msm8974pro-ac
52 compatible = "qcom,gcc-msm8974";
H A Dqcom,qdu1000-ecpricc.yaml30 - description: GPLL0 source from GCC
31 - description: GPLL1 source from GCC
32 - description: GPLL2 source from GCC
33 - description: GPLL3 source from GCC
34 - description: GPLL4 source from GCC
35 - description: GPLL5 source from GCC
54 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
60 <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
61 <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
62 <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-ipq9574.yaml90 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
94 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
120 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
121 <&gcc GCC_PCIE1_AXI_S_CLK>,
122 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
123 <&gcc GCC_PCIE1_RCHNG_CLK>,
124 <&gcc GCC_PCIE1_AHB_CLK>,
125 <&gcc GCC_PCIE1_AUX_CLK>;
133 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
134 <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
[all …]
H A Dqcom,pcie-ipq4019.yaml73 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
94 clocks = <&gcc GCC_PCIE_AHB_CLK>,
95 <&gcc GCC_PCIE_AXI_M_CLK>,
96 <&gcc GCC_PCIE_AXI_S_CLK>;
110 resets = <&gcc PCIE_AXI_M_ARES>,
111 <&gcc PCIE_AXI_S_ARES>,
112 <&gcc PCIE_PIPE_ARES>,
113 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
114 <&gcc PCIE_AXI_S_XPU_ARES>,
115 <&gcc PCIE_PARF_XPU_ARES>,
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,msm8996-mss-pil.yaml216 - description: GCC MSS IFACE clock
217 - description: GCC MSS BUS clock
218 - description: GCC MSS MEM clock
220 - description: GCC MSS GPLL0 clock
221 - description: GCC MSS SNOC_AXI clock
222 - description: GCC MSS MNOC_AXI clock
252 - description: GCC MSS IFACE clock
253 - description: GCC MSS BUS clock
254 - description: GCC MSS MEM clock
255 - description: GCC MSS GPLL0 clock
[all …]

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