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/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sm8150.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8150
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
15 power domains on SM8150.
18 - dt-bindings/clock/qcom,gcc-sm8150.h
22 const: qcom,gcc-sm8150
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Dqcom,gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
14 power domains on SDM845/SC7180/SM8150/SM8250.
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sm8150.h
20 dt-bindings/clock/qcom,gpucc-sm8250.h
25 - qcom,sdm845-gpucc
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Dqcom,rpmhcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <tdas@codeaurora.org>
20 - qcom,sc7180-rpmh-clk
21 - qcom,sdm845-rpmh-clk
22 - qcom,sm8150-rpmh-clk
23 - qcom,sm8250-rpmh-clk
28 clock-names:
30 - const: xo
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/linux-5.10/arch/arm64/boot/dts/qcom/
Dsm8150.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-aoss-qmp.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
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/linux-5.10/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
417 tristate "SM8150 and SM8250 Display Clock Controller"
421 SM8150 and SM8250 devices.
426 tristate "SM8150 Global Clock Controller"
428 Support for the global clock controller on SM8150 devices.
441 tristate "SM8150 Graphics Clock Controller"
444 Support for the graphics clock controller on SM8150 devices.
457 tristate "SM8150 Video Clock Controller"
461 Support for the video clock controller on SM8150 devices.
484 tristate "High-Frequency PLL (HFPLL) Clock Controller"
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Dgcc-sm8150.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
18 #include "clk-alpha-pll.h"
19 #include "clk-branch.h"
20 #include "clk-pll.h"
21 #include "clk-rcg.h"
22 #include "clk-regmap.h"
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/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,usb-snps-femto-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <wcheng@codeaurora.org>
13 Qualcomm High-Speed USB PHY
18 - qcom,usb-snps-hs-7nm-phy
19 - qcom,sm8150-usb-hs-phy
20 - qcom,usb-snps-femto-v2-phy
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Dqcom,qmp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
23 - qcom,msm8996-qmp-ufs-phy
24 - qcom,msm8996-qmp-usb3-phy
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/linux-5.10/Documentation/devicetree/bindings/firmware/
Dqcom,scm.txt9 - compatible: must contain one of the following:
10 * "qcom,scm-apq8064"
11 * "qcom,scm-apq8084"
12 * "qcom,scm-ipq4019"
13 * "qcom,scm-ipq806x"
14 * "qcom,scm-ipq8074"
15 * "qcom,scm-msm8660"
16 * "qcom,scm-msm8916"
17 * "qcom,scm-msm8960"
18 * "qcom,scm-msm8974"
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/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,osm-l3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <sibis@codeaurora.org>
20 - qcom,sc7180-osm-l3
21 - qcom,sdm845-osm-l3
22 - qcom,sm8150-osm-l3
23 - qcom,sm8250-epss-l3
30 - description: xo clock
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/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dqcom,apcs-kpss-global.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Sivaprakash Murugesan <sivaprak@codeaurora.org>
19 - qcom,ipq6018-apcs-apps-global
20 - qcom,ipq8074-apcs-apps-global
21 - qcom,msm8916-apcs-kpss-global
22 - qcom,msm8994-apcs-kpss-global
23 - qcom,msm8996-apcs-hmss-global
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/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
83 * if yes, then offset gives index in the reg-layout
115 /* set of registers with offsets different per-PHY */
1827 /* struct qmp_phy_cfg - per-PHY initialization config */
1829 /* phy-type - PCIE/UFS/USB */
1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1898 * struct qmp_phy - per-lane phy descriptor
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