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Searched +full:gcc +full:- +full:mdm9607 (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/clock/
Dqcom,gcc-mdm9607.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
18 include/dt-bindings/clock/qcom,gcc-mdm9607.h
21 - $ref: qcom,gcc.yaml#
26 - qcom,gcc-mdm9607
29 - compatible
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/linux-6.15/Documentation/devicetree/bindings/firmware/
Dqcom,scm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Bjorn Andersson <bjorn.andersson@linaro.org>
17 - Robert Marko <robimarko@gmail.com>
18 - Guru Das Srinagesh <quic_gurus@quicinc.com>
23 - enum:
24 - qcom,scm-apq8064
25 - qcom,scm-apq8084
26 - qcom,scm-ipq4019
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/linux-6.15/drivers/clk/qcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
4 clk-qcom-y += common.o
5 clk-qcom-y += clk-regmap.o
6 clk-qcom-y += clk-alpha-pll.o
7 clk-qcom-y += clk-pll.o
8 clk-qcom-y += clk-rcg.o
9 clk-qcom-y += clk-rcg2.o
10 clk-qcom-y += clk-branch.o
11 clk-qcom-y += clk-regmap-divider.o
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Dgcc-mdm9607.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/qcom,gcc-mdm9607.h>
19 #include "clk-regmap.h"
20 #include "clk-alpha-pll.h"
21 #include "clk-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
1591 { .compatible = "qcom,gcc-mdm9607" },
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
206 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
207 the output clocks to the networking hardware and GCC blocks.
361 tristate "MDM9607 Global Clock Controller"
364 Support for the global clock controller on mdm9607 devices.
1294 Say Y if you want to toggle LPASS-adjacent resets within
1393 tristate "High-Frequency PLL (HFPLL) Clock Controller"
1395 Support for the high-frequency PLLs present on Qualcomm devices.
1402 Support for the Krait ACC and GCC clock controllers. Say Y
/linux-6.15/drivers/thermal/qcom/
Dtsens.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/nvmem-consumer.h>
26 * struct tsens_irq_data - IRQ status and temperature violations
81 if (priv->num_sensors > MAX_SENSORS) in tsens_read_calibration()
82 return -EINVAL; in tsens_read_calibration()
88 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode); in tsens_read_calibration()
89 if (ret == -ENOENT) in tsens_read_calibration()
90 dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); in tsens_read_calibration()
94 dev_dbg(priv->dev, "calibration mode is %d\n", mode); in tsens_read_calibration()
100 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); in tsens_read_calibration()
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