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/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,gcc-apq8064.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
15 power domains on APQ8064.
18 - dt-bindings/clock/qcom,gcc-msm8960.h
19 - dt-bindings/reset/qcom,gcc-msm8960.h
[all …]
/linux-5.10/Documentation/devicetree/bindings/pci/
Dqcom,pcie.txt3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
[all …]
/linux-5.10/arch/arm/boot/dts/
Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/firmware/
Dqcom,scm.txt9 - compatible: must contain one of the following:
10 * "qcom,scm-apq8064"
11 * "qcom,scm-apq8084"
12 * "qcom,scm-ipq4019"
13 * "qcom,scm-ipq806x"
14 * "qcom,scm-ipq8074"
15 * "qcom,scm-msm8660"
16 * "qcom,scm-msm8916"
17 * "qcom,scm-msm8960"
18 * "qcom,scm-msm8974"
[all …]
/linux-5.10/Documentation/devicetree/bindings/soc/qcom/
Dqcom,gsbi.txt4 representing a serial sub-node device that is mux'd as part of the GSBI
9 - compatible: Should contain "qcom,gsbi-v1.0.0"
10 - cell-index: Should contain the GSBI index
11 - reg: Address range for GSBI registers
12 - clocks: required clock
13 - clock-names: must contain "iface" entry
14 - qcom,mode : indicates MUX value for configuration of the serial interface.
15 Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
18 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
19 dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
[all …]
/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom-apq8064-sata-phy.txt1 Qualcomm APQ8064 SATA PHY Controller
2 ------------------------------------
4 SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
8 - compatible: compatible list, contains "qcom,apq8064-sata-phy".
9 - reg: offset and length of the SATA PHY register set;
10 - #phy-cells: must be zero
11 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
12 clock-names.
13 - clock-names: must be "cfg" for phy config clock.
16 sata_phy: sata-phy@1b400000 {
[all …]
Dqcom,usb-hs-phy.txt5 - compatible:
8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
11 "qcom,usb-hs-phy-apq8064"
12 "qcom,usb-hs-phy-msm8916"
13 "qcom,usb-hs-phy-msm8974"
15 - #phy-cells:
20 - clocks:
22 Value type: <prop-encoded-array>
26 - clock-names:
32 - resets:
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/msm/
Dqcom,kpss-gcc.txt1 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
5 - compatible:
9 "qcom,kpss-gcc" should also be included.
10 "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
11 "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
12 "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
13 "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
15 - reg:
17 Value type: <prop-encoded-array>
20 - clocks:
[all …]
/linux-5.10/Documentation/devicetree/bindings/dma/
Dqcom_adm.txt4 - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
5 - reg: Address range for DMA registers
6 - interrupts: Should contain one interrupt shared by all channels
7 - #dma-cells: must be <2>. First cell denotes the channel number. Second cell
9 - clocks: Should contain the core clock and interface clock.
10 - clock-names: Must contain "core" for the core clock and "iface" for the
12 - resets: Must contain an entry for each entry in reset names.
13 - reset-names: Must include the following entries:
14 - clk
15 - c0
[all …]
Dqcom_bam_dma.txt4 - compatible: must be one of the following:
5 * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
6 * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
7 * "qcom,bam-v1.7.0" for MSM8916
8 - reg: Address range for DMA registers
9 - interrupts: Should contain the one interrupt shared by all channels
10 - #dma-cells: must be <1>, the cell in the dmas property of the client device
12 - clocks: required clock
13 - clock-names: must contain "bam_clk" entry
14 - qcom,ee : indicates the active Execution Environment identifier (0-7) used in
[all …]
/linux-5.10/drivers/clk/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 platforms such as apq8064, msm8660, msm8960 etc.
182 tristate "APQ8064/MSM8960 Global Clock Controller"
184 Support for the global clock controller on apq8064/msm8960 devices.
189 tristate "APQ8064/MSM8960 LPASS Clock Controller"
192 Support for the LPASS clock controller on apq8064/msm8960 devices.
484 tristate "High-Frequency PLL (HFPLL) Clock Controller"
486 Support for the high-frequency PLLs present on Qualcomm devices.
493 Support for the Krait ACC and GCC clock controllers. Say Y
495 as MSM8960, APQ8064, etc.
Dgcc-msm8960.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
13 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
18 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
[all …]