| /linux-6.8/drivers/nvmem/ |
| D | apple-efuses.c | 15 void __iomem *fuses; member
25 *dst++ = readl_relaxed(priv->fuses + offset); in apple_efuses_read()
53 priv->fuses = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in apple_efuses_probe()
54 if (IS_ERR(priv->fuses)) in apple_efuses_probe()
55 return PTR_ERR(priv->fuses); in apple_efuses_probe()
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| D | qfprom.c | 152 * when we're not blowing fuses. At the moment, the regulator framework in qfprom_disable_fuse_blowing()
246 * qfprom_reg_write() - Write to fuses.
252 * Writes to fuses. WARNING: THIS IS PERMANENT.
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| /linux-6.8/drivers/crypto/intel/qat/qat_c3xxx/ |
| D | adf_c3xxx_hw_data.c | 30 u32 fuses = self->fuses; in get_accel_mask() local
33 accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET; in get_accel_mask()
42 u32 fuses = self->fuses; in get_ae_mask() local
53 return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK; in get_ae_mask()
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| /linux-6.8/drivers/crypto/intel/qat/qat_c62x/ |
| D | adf_c62x_hw_data.c | 30 u32 fuses = self->fuses; in get_accel_mask() local
33 accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET; in get_accel_mask()
42 u32 fuses = self->fuses; in get_ae_mask() local
53 return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK; in get_ae_mask()
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| D | adf_drv.c | 129 &hw_data->fuses); in adf_probe()
172 i = (hw_data->fuses & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0; in adf_probe()
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| /linux-6.8/drivers/crypto/intel/qat/qat_dh895xcc/ |
| D | adf_dh895xcc_hw_data.c | 31 u32 fuses = self->fuses; in get_accel_mask() local
33 return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & in get_accel_mask()
39 u32 fuses = self->fuses; in get_ae_mask() local
41 return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK; in get_ae_mask()
101 int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK) in get_sku()
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| /linux-6.8/drivers/pmdomain/qcom/ |
| D | cpr.c | 808 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_populate_ring_osc_idx() local
812 for (; fuse < end; fuse++, fuses++) { in cpr_populate_ring_osc_idx()
813 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); in cpr_populate_ring_osc_idx()
850 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_fuse_corner_init() local
871 for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) { in cpr_fuse_corner_init()
881 uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage, in cpr_fuse_corner_init()
901 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); in cpr_fuse_corner_init()
1078 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_corner_init() local
1176 quot_offset = fuses[fnum].quotient_offset; in cpr_corner_init()
1229 struct cpr_fuse *fuses; in cpr_get_fuses() local
[all …]
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| /linux-6.8/drivers/crypto/intel/qat/qat_common/ |
| D | adf_gen2_hw_data.c | 216 u32 fuses = hw_data->fuses; in adf_gen2_get_accel_cap() local
241 if ((straps | fuses) & ADF_POWERGATE_PKE) in adf_gen2_get_accel_cap()
244 if ((straps | fuses) & ADF_POWERGATE_DC) in adf_gen2_get_accel_cap()
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| D | adf_gen4_hw_data.h | 20 /* Physical function fuses */
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| /linux-6.8/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra20-usb-phy.yaml | 167 nvidia,xcvr-setup-use-fuses:
168 description: Indicates that the value is read from the on-chip fuses.
254 - required: ["nvidia,xcvr-setup-use-fuses"]
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| /linux-6.8/Documentation/devicetree/bindings/iio/adc/ |
| D | microchip,mcp3564.yaml | 84 The address is set on a per-device basis by fuses in the factory,
85 configured on request. If not requested, the fuses are set for 0x1.
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| /linux-6.8/Documentation/devicetree/bindings/cpufreq/ |
| D | imx-cpufreq-dt.txt | 5 "speed grading" value which are written in fuses. These bits are combined with
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| /linux-6.8/arch/mips/cavium-octeon/executive/ |
| D | octeon-model.c | 461 /* Check for model in fuses, overrides normal decode */ in octeon_model_get_string_buffer()
474 /* Have both number and suffix in fuses, so both */ in octeon_model_get_string_buffer()
483 /* Don't have suffix, so just use model from fuses */ in octeon_model_get_string_buffer()
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| /linux-6.8/drivers/soc/qcom/ |
| D | ice.c | 69 /* If fuses are blown, ICE might not work in the standard way. */ in qcom_ice_check_supported()
74 dev_warn(dev, "Fuses are blown; ICE is unusable!\n"); in qcom_ice_check_supported()
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| /linux-6.8/drivers/rtc/ |
| D | rtc-stmp3xxx.c | 303 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality in stmp3xxx_rtc_probe()
304 * proves these fuses are not blown correctly on all machines, so the in stmp3xxx_rtc_probe()
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| /linux-6.8/drivers/thermal/tegra/ |
| D | soctherm.h | 99 * calibration fuses
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| /linux-6.8/drivers/bus/ |
| D | intel-ixp4xx-eb.c | 69 /* Fuses on the IXP43x */
377 /* Check some fuses */ in ixp4xx_exp_probe()
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| /linux-6.8/drivers/platform/mellanox/ |
| D | mlxbf-bootctl.h | 68 * with the second argument if the state of the lifecycle fuses or the
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| /linux-6.8/drivers/soc/tegra/fuse/ |
| D | speedo-tegra210.c | 116 /* Read speedo/IDDQ fuses */ in tegra210_init_speedo_data()
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| /linux-6.8/drivers/cpufreq/ |
| D | imx-cpufreq-dt.c | 136 * Early samples without fuses written report "0 0" which may NOT in imx_cpufreq_dt_probe()
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| /linux-6.8/drivers/soc/imx/ |
| D | soc-imx8m.c | 77 * SOC revision on older imx8mq is not available in fuses so query in imx8mq_soc_revision()
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| /linux-6.8/drivers/crypto/intel/qat/qat_4xxx/ |
| D | adf_drv.c | 84 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses); in adf_probe()
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| /linux-6.8/drivers/gpu/drm/i915/gt/uc/ |
| D | guc_capture_fwif.h | 180 * (slices or dual-sub-slices) and thus depends on HW fuses discovered at startup
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| /linux-6.8/drivers/crypto/intel/qat/qat_420xx/ |
| D | adf_drv.c | 82 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses); in adf_probe()
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| /linux-6.8/drivers/thermal/ |
| D | rcar_gen3_thermal.c | 315 /* If fuses are not set, fallback to pseudo values. */ in rcar_gen3_thermal_read_fuses()
319 /* Default THCODE values in case FUSEs are not set. */ in rcar_gen3_thermal_read_fuses()
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