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/qemu/hw/arm/
H A Dmeson.build39 arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
40 arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
41 arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
60 arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c'))
61 arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'))
64 arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
H A Dfsl-imx31.c6 * Based on hw/arm/fsl-imx31.c
24 #include "hw/arm/fsl-imx31.h"
H A Dmcimx7d-sabre.c17 #include "hw/arm/fsl-imx7.h"
H A Dmcimx6ul-evk.c15 #include "hw/arm/fsl-imx6ul.h"
H A Dimx8mp-evk.c12 #include "hw/arm/fsl-imx8mp.h"
H A Dsabrelite.c15 #include "hw/arm/fsl-imx6.h"
H A Dkzm.c18 #include "hw/arm/fsl-imx31.h"
H A Dimx25_pdk.c29 #include "hw/arm/fsl-imx25.h"
H A Dfsl-imx6.c6 * Based on hw/arm/fsl-imx31.c
24 #include "hw/arm/fsl-imx6.h"
H A Dfsl-imx6ul.c6 * Based on hw/arm/fsl-imx7.c
21 #include "hw/arm/fsl-imx6ul.h"
H A Dfsl-imx7.c8 * Based on hw/arm/fsl-imx6.c
23 #include "hw/arm/fsl-imx7.h"
/qemu/include/hw/ppc/
H A Dopenpic.h50 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
51 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
76 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
94 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
137 FslMpicInfo *fsl; member
/qemu/pc-bios/dtb/
H A Dpetalogix-s3adsp1800.dts59 xlnx,dcache-use-fsl = <0x01>;
67 xlnx,fsl-data-size = <0x20>;
68 xlnx,fsl-exception = <0x00>;
69 xlnx,fsl-links = <0x00>;
75 xlnx,icache-use-fsl = <0x01>;
100 xlnx,use-extended-fsl-instr = <0x00>;
255 xlnx,write-fsl-ports = <0x00>;
H A Dpetalogix-ml605.dts68 xlnx,dcache-use-fsl = < 0x00 >;
81 xlnx,fsl-data-size = < 0x20 >;
82 xlnx,fsl-exception = < 0x00 >;
83 xlnx,fsl-links = < 0x00 >;
93 xlnx,icache-use-fsl = < 0x00 >;
122 xlnx,use-extended-fsl-instr = < 0x00 >;
/qemu/pc-bios/
HDu-boot.e500__of_translate_address fdt_fixup_memory_banks set_tlb do_bootvx_fdt dev_get_parent_priv device_remove mpc85xx_pci_dm_probe tsec_mdio_probe phy_device_create fs_devread dev_get_uclass_priv virtio_uclass_child_pre_probe virtio_has_feature virtio_pci_set_status virtio_pci_get_config virtio_has_feature dev_get_priv virtqueue_add virtio_pci_set_features ...
/qemu/hw/ppc/
H A De500.c161 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); in create_dt_mpc8xxx_gpio()
202 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); in dt_i2c_create()
228 qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc"); in dt_sdhc_create()
259 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); in create_devtree_etsec()
388 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; in ppce500_load_device_tree()
550 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); in ppce500_load_device_tree()
588 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); in ppce500_load_device_tree()
590 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); in ppce500_load_device_tree()
595 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); in ppce500_load_device_tree()
617 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); in ppce500_load_device_tree()
[all …]
H A De500plat.c26 const char compatible[] = "fsl,qemu-e500"; in e500plat_fixup_devtree()
/qemu/include/hw/pci-host/
H A Dfsl_imx8m_phy.h16 #define TYPE_FSL_IMX8M_PCIE_PHY "fsl-imx8m-pcie-phy"
/qemu/hw/pci-host/
H A Dfsl_imx8m_phy.c69 .name = "fsl-imx8m-pcie-phy",
/qemu/include/hw/arm/
H A Dfsl-imx31.h32 #define TYPE_FSL_IMX31 "fsl-imx31"
H A Dfsl-imx8mp.h33 #define TYPE_FSL_IMX8MP "fsl-imx8mp"
H A Dfsl-imx6ul.h41 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
H A Dfsl-imx7.h44 #define TYPE_FSL_IMX7 "fsl-imx7"
H A Dfsl-imx25.h36 #define TYPE_FSL_IMX25 "fsl-imx25"
/qemu/hw/intc/
H A Dopenpic.c508 * NOTE when implementing newer FSL MPIC models: starting with v4.0, in write_IRQreg_ivpr()
519 * For FSL internal interrupts, The sense bit is reserved and zero, in write_IRQreg_ivpr()
1348 for (i = 0; i < opp->fsl->max_ext; i++) { in fsl_common_init()
1545 opp->fsl = &fsl_mpic_20; in openpic_realize()
1558 opp->fsl = &fsl_mpic_42; in openpic_realize()

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