front\-end (full) in projects: linux-6.8

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/linux-6.8/tools/perf/pmu-events/arch/x86/rocketlake/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/tigerlake/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/icelakex/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/icelake/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 24 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 43 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 54 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 92 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/emeraldrapids/
D	frontend.json	6 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 26 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 29 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 40 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 51 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 89 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 95 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 100 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 106 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	frontend.json	6 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 26 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 29 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 40 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 51 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 89 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 95 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 100 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 106 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/alderlake/
D	frontend.json	15 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 53 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 65 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 107 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 113 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 119 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 125 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/meteorlake/
D	frontend.json	15 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio… 24 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 38 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 41 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 73 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 85 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 136 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 142 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n… 148 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … 154 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not … [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/cascadelakex/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/skylakex/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/skylake/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 14 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 22 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea… 27 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 30 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th… 41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 52 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th… 88 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/silvermont/
D	frontend.json	6 …front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction… 14 …front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction… 22 …front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction… 59 …s entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults … 62 …e most common case that this counts is when a micro-coded instruction is encountered by the front …
D	pipeline.json	96 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 104 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 113 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 122 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 131 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 140 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp… 184 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last … 192 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last… 199 …front end of the machine is notified that it must restart, so no more instructions will be decoded… 204 "BriefDescription": "Self-Modifying Code detected", [all …]
/linux-6.8/Documentation/admin-guide/
D	pstore-blk.rst	1 .. SPDX-License-Identifier: GPL-2.0 7 ------------ 10 block device and non-block device before the system crashes. You can get 13 mount -t pstore pstore /sys/fs/pstore 17 --------------------- 27 Configurations for driver are all about block device and non-block device, 31 ----------------------- 51 #. /dev/<disk_name><decimal> represents the device number of partition - device 53 #. /dev/<disk_name>p<decimal> - same as the above; this form is used when disk 60 #. PARTUUID=00112233-4455-6677-8899-AABBCCDDEEFF represents the unique id of [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/goldmont/
D	pipeline.json	214 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 222 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 287 "BriefDescription": "Self-Modifying Code detected", 290 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 295 "BriefDescription": "Uops issued to the back end per cycle", 298 …front end and allocated into the back end of the machine. This event counts uops that retire as w… 302 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 305 …front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-en… 330 …ued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uop…
/linux-6.8/tools/perf/pmu-events/arch/x86/goldmontplus/
D	pipeline.json	205 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature", 223 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.… 231 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r… 299 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store… 304 "BriefDescription": "Self-Modifying Code detected", 307 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) … 312 "BriefDescription": "Uops issued to the back end per cycle", 315 …front end and allocated into the back end of the machine. This event counts uops that retire as w… 319 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", 322 …front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-en… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/haswellx/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 25 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 136 …s event counts cycles during which the microcode sequencer assisted the Front-end in delivering uo… 186 …"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the… 195 …Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalle… 205 …Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of… 229 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/haswell/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 25 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 32 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 136 …s event counts cycles during which the microcode sequencer assisted the Front-end in delivering uo… 186 …"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the… 195 …Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalle… 205 …Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of… 229 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", [all …]
/linux-6.8/drivers/media/i2c/
D	ccs-pll.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 drivers/media/i2c/ccs-pll.h 17 /* CSI-2 or CCP-2 / 37 struct ccs_pll_branch_fr - CCS PLL configuration (front) 39 * A single branch front-end of the CCS PLL tree. 41 * @pre_pll_clk_div: Pre-PLL clock divisor 54 * struct ccs_pll_branch_bk - CCS PLL configuration (back) 56 * A single branch back-end of the CCS PLL tree. 71 * struct ccs_pll - Full CCS PLL configuration 78 * @csi2: CSI-2 related parameters [all …]`
/linux-6.8/include/media/
D	demux.h	4 * The Kernel Digital TV Demux kABI defines a driver-internal interface for 5 * registering low-level, hardware specific driver to a hardware independent 64 * enum ts_filter_type - filter type bitmap for dmx_ts_feed.set\(\) 69 * @TS_DECODER: Send stream to built-in decoder (if present). 81 * struct dmx_ts_feed - Structure that contains a TS feed filter 83 * @is_filtering: Set to non-zero when filtering in progress 112 * struct dmx_section_filter - Structure that describes a section filter 120 * @parent: Back-pointer to struct dmx_section_feed. 139 * struct dmx_section_feed - Structure that contains a section feed filter 141 * @is_filtering: Set to non-zero when filtering in progress [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/sandybridge/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 20 …-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles o… 141 …front-end in delivering uops. Microcode assists are used for complex instructions or scenarios th… 196 …-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be de… 218 "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", 235 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 243 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
/linux-6.8/tools/perf/pmu-events/arch/x86/jaketown/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 10 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 17 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 20 …-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles o… 141 …front-end in delivering uops. Microcode assists are used for complex instructions or scenarios th… 196 …-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be de… 218 "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", 235 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 243 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
/linux-6.8/include/xen/interface/io/
D	ring.h	`1 /* SPDX-License-Identifier: MIT / 5 Shared producer-consumer ring macros. 16 * - standard integers types (uint8_t, uint16_t, etc) 21 * - size_t 22 * - memcpy 23 * - grant_ref_t 32 /* Round a 32-bit unsigned constant down to the nearest power of two. / 43 power of two (so we can mask with (size-1) to loop around). 46 (__RD32(((_sz) - offsetof(struct _s##_sring, ring)) / \ 47 sizeof(((struct _s##_sring *)0)->ring[0]))) [all …]`
/linux-6.8/tools/perf/pmu-events/arch/x86/ivytown/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 43 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 46 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 210 …pipeline slots where no uop was delivered from the front end to the back end when there is no back… 240 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 248 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
/linux-6.8/tools/perf/pmu-events/arch/x86/ivybridge/
D	frontend.json	3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc… 6 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 43 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 46 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 210 …pipeline slots where no uop was delivered from the front end to the back end when there is no back… 240 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 248 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",

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