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/src/crypto/openssl/include/internal/
H A Dquic_fc.h2 * Copyright 2022-2024 The OpenSSL Project Authors. All Rights Reserved.
19 * TX Flow Controller (TXFC)
22 * For discussion, see doc/designs/quic-design/quic-fc.md.
27 QUIC_TXFC *parent; /* stream-level iff non-NULL */
33 * Initialises a TX flow controller. conn_txfc should be non-NULL and point to
34 * the connection-level flow controller if the TXFC is for stream-level flow
40 * Gets the parent (i.e., connection-level) TX flow controller. Returns NULL if
41 * called on a connection-level TX flow controller.
47 * operation. This function is a no-op if it has already been called with an
62 * If called on a stream-level TXFC, ossl_quic_txfc_get_credit is called on
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/src/crypto/openssl/doc/designs/quic-design/
H A Dquic-fc.md1 Flow Control
4 Introduction to QUIC Flow Control
5 ---------------------------------
7 QUIC flow control acts at both connection and stream levels. At any time,
8 transmission of stream data could be prevented by connection-level flow control,
9 by stream-level flow control, or both. Flow control uses a credit-based model in
10 which the relevant flow control limit is expressed as the maximum number of
14 It is important to note that both connection and stream-level flow control
15 relate only to the transmission of QUIC stream data. QUIC flow control at stream
18 again, this still only counts as one byte for the purposes of flow control. Note
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H A Dquic-overview.md7 ![alt_text](images/quic-overview.svg "QUIC Implementation Building Blocks")
10 -------
15 ----------------------------
21 They will be bypassed with a single-copy API for read and write (_not
25 -----------------------
29 [discussed in more detail here.](./quic-fifm.md)
32 ------------------------
37 -------------------
42 _In MVP there is a many-to-1 matching of Connection IDs to Connection
45 [5.1]: (https://datatracker.ietf.org/doc/html/rfc9000#section-5.1)
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H A Dstream-receive-buffers.md9 ------------------------------------
13 - As packets with stream frames are received in arbitrary frames the
16 - As packets can be received before application calls SSL_read() to read
18 - The application should be able to set the limit on how much data should
19 be stored. The flow controller should be used to limit the peer to not send
20 more data. Without the flow control limit a rogue peer could trigger
21 a DoS via unlimited flow of incoming stream data frames.
22 - After the data is passed via SSL_read() to the application the stored
23 data can be released and flow control limit can be raised.
24 - As the peer can recreate stream data frames when resending them, the
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H A Dtx-packetiser.md9 The packetiser also deals with the flow and congestion controllers.
12 ----------------------
29 QUIC_TXFC *conn_txfc; /* QUIC Connection-Level TX Flow Controller */
30 QUIC_RXFC *conn_rxfc; /* QUIC Connection-Level RX Flow Controller */
31 const OSSL_CC_METHOD *cc_method; /* QUIC Congestion Controller */
32 OSSL_CC_DATA *cc_data; /* QUIC Congestion Controller Instance */
37 * Injected dependencies - crypto streams.
39 * Note: There is no crypto stream for the 0-RTT EL.
40 * crypto[QUIC_PN_SPACE_APP] is the 1-RTT crypto stream.
52 ----------
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/src/sys/contrib/device-tree/Bindings/net/nfc/
H A Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell International Ltd. NCI NFC controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
30 reset-n-io:
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H A Dnfcmrvl.txt1 * Marvell International Ltd. NCI NFC Controller
4 - compatible: Should be:
5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
6 - "marvell,nfc-i2c" for I2C devices
7 - "marvell,nfc-spi" for SPI devices
10 - pinctrl-names: Contains only one value - "default".
11 - pintctrl-0: Specifies the pin control groups used for this controller.
12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
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/src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dcirrus,ep7209-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/cirrus,ep7209-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic CLPS711X Interrupt Controller
10 - Alexander Shiyan <shc_work@mail.ru>
13 Cirrus Logic CLPS711X Interrupt Controller
17 ---------------------------
24 8: TC1OI TC1 under flow
25 9: TC2OI TC2 under flow
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H A Dcirrus,clps711x-intc.txt1 Cirrus Logic CLPS711X Interrupt Controller
5 - compatible: Should be "cirrus,ep7209-intc".
6 - reg: Specifies base physical address of the registers set.
7 - interrupt-controller: Identifies the node as an interrupt controller.
8 - #interrupt-cells: Specifies the number of cells needed to encode an
13 ---------------------------
20 8: TC1OI TC1 under flow
21 9: TC2OI TC2 under flow
36 intc: interrupt-controller {
37 compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
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/src/sys/contrib/device-tree/Bindings/dma/
H A Dqcom_adm.txt1 QCOM ADM DMA Controller
4 - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
5 - reg: Address range for DMA registers
6 - interrupts: Should contain one interrupt shared by all channels
7 - #dma-cells: must be <2>. First cell denotes the channel number. Second cell
8 denotes CRCI (client rate control interface) flow control assignment.
9 - clocks: Should contain the core clock and interface clock.
10 - clock-names: Must contain "core" for the core clock and "iface" for the
12 - resets: Must contain an entry for each entry in reset names.
13 - reset-names: Must include the following entries:
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/src/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-flowctrl.txt1 NVIDIA Tegra Flow Controller
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra20-flowctrl": for Tegra20
6 - "nvidia,tegra30-flowctrl": for Tegra30
7 - "nvidia,tegra114-flowctrl": for Tegra114
8 - "nvidia,tegra124-flowctrl": for Tegra124
9 - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
10 - "nvidia,tegra210-flowctrl": for Tegra210
11 - reg: Should contain one register range (address and length)
15 flow-controller@60007000 {
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/src/share/man/man4/
H A Diavf.41 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2013-2018, Intel Corporation
44 .Bd -ragged -offset indent
51 .Bd -literal -offset indent
62 .Bl -bullet -compact
64 Intel\(rg Ethernet Controller E810\-C
66 Intel\(rg Ethernet Controller E810\-XXV
68 Intel\(rg Ethernet Connection E822\-C
70 Intel\(rg Ethernet Connection E822\-L
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H A Dirdma.41 .\" Copyright(c) 2016 - 2022 Intel Corporation
14 .\" - Redistributions of source code must retain the above
18 .\" - Redistributions in binary form must reproduce the above
37 .Nd RDMA FreeBSD driver for Intel(R) Ethernet Controller E810
41 .Bl -tag -width indent
53 driver provides RDMA protocol support on RDMA-capable Intel Ethernet 800 Series
65 .Bl -tag -width indent
84 Value is given as a percentage (1-100).
120 The minimum time between 2 consecutive rate reductions for a single flow.
129 .Bl -tag -width indent
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/src/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-flowctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-flowctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Flow Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-flowctrl
18 - nvidia,tegra30-flowctrl
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/src/sys/contrib/device-tree/Bindings/crypto/
H A Damlogic,gxl-crypto.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Corentin Labbe <clabbe@baylibre.com>
15 - const: amlogic,gxl-crypto
22 - description: Interrupt for flow 0
23 - description: Interrupt for flow 1
28 clock-names:
32 - compatible
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/src/sys/contrib/device-tree/Bindings/serial/
H A Dmilbeaut-uart.txt1 Socionext Milbeaut UART controller
4 - compatible: should be "socionext,milbeaut-usio-uart".
5 - reg: offset and length of the register set for the device.
6 - interrupts: two interrupts specifier.
7 - interrupt-names: should be "rx", "tx".
8 - clocks: phandle to the input clock.
11 - auto-flow-control: flow control enable.
15 compatible = "socionext,milbeaut-usio-uart";
18 interrupt-names = "rx", "tx";
20 auto-flow-control;
H A Dsocionext,milbeaut-usio-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/socionext,milbeaut-usio-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext Milbeaut UART controller
10 - Sugaya Taichi <sugaya.taichi@socionext.com>
13 - $ref: /schemas/serial/serial.yaml#
17 const: socionext,milbeaut-usio-uart
24 - description: RX interrupt specifier
25 - description: TX interrupt specifier
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H A Dsocionext,uniphier-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier UART controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 const: socionext,uniphier-uart
28 auto-flow-control:
29 description: enable automatic flow control support.
33 - compatible
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H A Dst,asc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 - $ref: serial.yaml#
28 st,hw-flow-ctrl:
29 description: When set, enable hardware flow control.
32 st,force-m1:
33 description: When set, force asc to be in Mode-1. This is recommended for
38 - compatible
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/src/sys/contrib/device-tree/Bindings/net/
H A Dairoha,en7581-eth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 Frame Engine Ethernet controller
10 - Lorenzo Bianconi <lorenzo@kernel.org>
13 The frame engine ethernet controller can be found on Airoha SoCs.
14 These SoCs have multi-GMAC ports.
19 - airoha,en7581-eth
23 - description: Frame engine base address
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H A Dairoha,en7581-npu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/airoha,en7581-npu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
14 to implement wired and wireless hardware flow offloading programming Packet
15 Processor Engine (PPE) flow table.
20 - airoha,en7581-npu
27 - description: mbox host irq line
28 - description: watchdog0 irq line
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/src/sys/contrib/device-tree/Bindings/hsi/
H A Dclient-devices.txt7 - hsi-channel-ids: A list of channel ids
9 - hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame")
10 - hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame")
11 - hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if
14 - hsi-speed-kbps: Max bit transmission speed in kbit/s
15 - hsi-flow: RX flow type ("synchronized" or "pipeline")
16 - hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority")
20 - hsi-channel-names: A list with one name per channel specified in the
21 hsi-channel-ids property
26 hsi-controller {
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/src/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos850-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
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/src/sys/netpfil/ipfw/test/
H A Dmain.c5 * The framework include a simple controller which, at each
30 int32_t th_min, th_max; /* thresholds for hysteresis; negative means per flow */
41 int cur_fs; /* used in generation, between 0 and max_y - 1 */
46 struct mbuf *tosend; /* packet to send -- also flag to enqueue */
56 /* size of the three fields including sched-specific areas */
58 uint32_t q_len; /* size of a queue including sched-fields */
59 uint32_t si_len; /* size of a sch_inst including sched-fields */
60 char *q; /* array of flow queues */
64 * for scheduler-specific parameters, total size is schk_len
70 * total size is si_len. si->sched points to sched
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/src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-sirf.txt1 CSR SiRFprimaII pinmux controller
4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
19 Required subnode-properties:
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