| /linux-3.3/kernel/ |
| D | kfifo.c | 2 * A generic kernel FIFO implementation
31 * internal helper to calculate the unused elements in a fifo
33 static inline unsigned int kfifo_unused(struct __kfifo *fifo) in kfifo_unused() argument
35 return (fifo->mask + 1) - (fifo->in - fifo->out); in kfifo_unused()
38 int __kfifo_alloc(struct __kfifo *fifo, unsigned int size, in __kfifo_alloc() argument
48 fifo->in = 0; in __kfifo_alloc()
49 fifo->out = 0; in __kfifo_alloc()
50 fifo->esize = esize; in __kfifo_alloc()
53 fifo->data = NULL; in __kfifo_alloc()
54 fifo->mask = 0; in __kfifo_alloc()
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| /linux-3.3/include/linux/ |
| D | kfifo.h | 2 * A generic kernel FIFO implementation
26 * How to porting drivers to the new generic FIFO API:
45 * and one writer is using the fifo and no kfifo_reset() will be * called
111 * helper macro to distinguish between real in place fifo where the fifo
112 * array is a part of the structure and the fifo type where the array is
113 * outside of the fifo structure.
115 #define __is_kfifo_ptr(fifo) (sizeof(*fifo) == sizeof(struct __kfifo)) argument
118 * DECLARE_KFIFO_PTR - macro to declare a fifo pointer object
119 * @fifo: name of the declared fifo
120 * @type: type of the fifo elements
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| D | serial_reg.h | 43 #define UART_FCR 2 /* Out: FIFO Control Register */
44 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
45 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
46 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
49 * Note: The FIFO trigger levels are chip specific:
71 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
122 #define UART_LSR_FIFOE 0x80 /* Fifo error */
182 * In: Fifo count
183 * Out: Fifo custom trigger levels */
229 #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */
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| D | pxa2xx_ssp.h | 59 #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
60 #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
63 #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
68 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
69 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
76 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
77 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
79 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
80 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
81 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
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| /linux-3.3/drivers/usb/renesas_usbhs/ |
| D | fifo.c | 234 * FIFO ctrl
237 struct usbhs_fifo *fifo) in usbhsf_send_terminator() argument
241 usbhs_bset(priv, fifo->ctr, BVAL, BVAL); in usbhsf_send_terminator()
245 struct usbhs_fifo *fifo) in usbhsf_fifo_barrier() argument
250 /* The FIFO port is accessible */ in usbhsf_fifo_barrier()
251 if (usbhs_read(priv, fifo->ctr) & FRDY) in usbhsf_fifo_barrier()
261 struct usbhs_fifo *fifo) in usbhsf_fifo_clear() argument
266 usbhsf_fifo_barrier(priv, fifo); in usbhsf_fifo_clear()
268 usbhs_write(priv, fifo->ctr, BCLR); in usbhsf_fifo_clear()
272 struct usbhs_fifo *fifo) in usbhsf_fifo_rcv_len() argument
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| /linux-3.3/drivers/isdn/hisax/ |
| D | hfc_usb.c | 143 struct usb_fifo *owner_fifo; /* pointer to owner fifo */
149 int fifonum; /* fifo index attached to this structure */
150 int active; /* fifo is currently active */
159 int bit_line; /* how much bits are in the fifo? */
201 usb_fifo fifos[HFCUSB_NUM_FIFOS]; /* structure holding all fifo data */
209 static void collect_rx_frame(usb_fifo * fifo, __u8 * data, int len,
454 start_isoc_chain(usb_fifo * fifo, int num_packets_per_urb, in start_isoc_chain() argument
459 DBG(HFCUSB_DBG_INIT, "HFC-S USB: starting ISO-URBs for fifo:%d\n", in start_isoc_chain()
460 fifo->fifonum); in start_isoc_chain()
464 if (!(fifo->iso[i].purb)) { in start_isoc_chain()
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| D | st5481.h | 63 #define IN_D_COUNTER 0x36 /* D receive channel fifo counter */
64 #define OUT_D_COUNTER 0x37 /* D transmit channel fifo counter */
65 #define IN_B1_COUNTER 0x38 /* B1 receive channel fifo counter */
66 #define OUT_B1_COUNTER 0x39 /* B1 transmit channel fifo counter */
67 #define IN_B2_COUNTER 0x3a /* B2 receive channel fifo counter */
68 #define OUT_B2_COUNTER 0x3b /* B2 transmit channel fifo counter */
69 #define FFCTRL_IN_D 0x3C /* D receive channel fifo threshold low */
70 #define FFCTRH_IN_D 0x3D /* D receive channel fifo threshold high */
71 #define FFCTRL_OUT_D 0x3E /* D transmit channel fifo threshold low */
72 #define FFCTRH_OUT_D 0x3F /* D transmit channel fifo threshold high */
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| /linux-3.3/sound/core/seq/ |
| D | seq_fifo.h | 2 * ALSA sequencer FIFO
28 /* === FIFO === */
31 struct snd_seq_pool *pool; /* FIFO pool */
32 struct snd_seq_event_cell *head; /* pointer to head of fifo */
33 struct snd_seq_event_cell *tail; /* pointer to tail of fifo */
42 /* create new fifo (constructor) */
45 /* delete fifo (destructor) */
49 /* enqueue event to fifo */
52 /* lock fifo from release */
53 #define snd_seq_fifo_lock(fifo) snd_use_lock_use(&(fifo)->use_lock) argument
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| /linux-3.3/drivers/isdn/hardware/mISDN/ |
| D | hfcsusb.c | 721 conhdlc = 8; /* enable FIFO */ in hfcsusb_setup_bch()
829 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */ in channel_bctrl()
845 hfcsusb_rx_frame(struct usb_fifo *fifo, __u8 *data, unsigned int len, in hfcsusb_rx_frame() argument
848 struct hfcsusb *hw = fifo->hw; in hfcsusb_rx_frame()
851 int fifon = fifo->fifonum; in hfcsusb_rx_frame()
856 printk(KERN_DEBUG "%s: %s: fifo(%i) len(%i) " in hfcsusb_rx_frame()
859 fifo->dch, fifo->bch, fifo->ech); in hfcsusb_rx_frame()
864 if ((!!fifo->dch + !!fifo->bch + !!fifo->ech) != 1) { in hfcsusb_rx_frame()
871 if (fifo->dch) { in hfcsusb_rx_frame()
872 rx_skb = fifo->dch->rx_skb; in hfcsusb_rx_frame()
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| /linux-3.3/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5121-psc.txt | 8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is requered there:
19 PSC FIFO Controller and b is a field that represents an
25 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
26 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
29 fsl,mpc5121-psc-fifo node
33 - compatible : Should be "fsl,mpc5121-psc-fifo"
35 FIFO Controller
37 PSC FIFO Controller and b is a field that represents an
51 fsl,rx-fifo-size = <16>;
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| /linux-3.3/arch/arm/mach-pxa/include/mach/ |
| D | regs-ac97.h | 11 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
12 #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
15 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
16 #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
19 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
20 #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
39 #define POSR_FIFOE (1 << 4) /* FIFO error */
40 #define POSR_FSR (1 << 2) /* FIFO Service Request */
43 #define PISR_FIFOE (1 << 4) /* FIFO error */
45 #define PISR_FSR (1 << 2) /* FIFO Service Request */
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| /linux-3.3/drivers/gpu/drm/nouveau/ |
| D | nouveau_state.c | 69 engine->fifo.channels = 16; in nouveau_init_engine_ptrs()
70 engine->fifo.init = nv04_fifo_init; in nouveau_init_engine_ptrs()
71 engine->fifo.takedown = nv04_fifo_fini; in nouveau_init_engine_ptrs()
72 engine->fifo.disable = nv04_fifo_disable; in nouveau_init_engine_ptrs()
73 engine->fifo.enable = nv04_fifo_enable; in nouveau_init_engine_ptrs()
74 engine->fifo.reassign = nv04_fifo_reassign; in nouveau_init_engine_ptrs()
75 engine->fifo.cache_pull = nv04_fifo_cache_pull; in nouveau_init_engine_ptrs()
76 engine->fifo.channel_id = nv04_fifo_channel_id; in nouveau_init_engine_ptrs()
77 engine->fifo.create_context = nv04_fifo_create_context; in nouveau_init_engine_ptrs()
78 engine->fifo.destroy_context = nv04_fifo_destroy_context; in nouveau_init_engine_ptrs()
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| /linux-3.3/arch/unicore32/include/mach/ |
| D | regs-spi.h | 39 * Transmit FIFO Not Full SPI_SR_TFNF
43 * Transmit FIFO Empty SPI_SR_TFE
47 * Receive FIFO Not Empty SPI_SR_RFNE
51 * Receive FIFO Full SPI_SR_RFF
56 * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS
60 * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS
64 * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS
68 * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS
72 * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS
78 * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM
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| /linux-3.3/samples/kfifo/ |
| D | dma-example.c | 2 * Sample fifo dma implementation
15 * This module shows how to handle fifo dma operations.
18 /* fifo size in elements (bytes) */
21 static struct kfifo fifo; variable
30 printk(KERN_INFO "DMA fifo test start\n"); in example_init()
32 if (kfifo_alloc(&fifo, FIFO_SIZE, GFP_KERNEL)) { in example_init()
37 printk(KERN_INFO "queue size: %u\n", kfifo_size(&fifo)); in example_init()
39 kfifo_in(&fifo, "test", 4); in example_init()
42 kfifo_put(&fifo, &i); in example_init()
45 kfifo_skip(&fifo); in example_init()
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| D | bytestream-example.c | 17 * This module shows how to create a byte stream fifo.
20 /* fifo size in elements (bytes) */
24 #define PROC_FIFO "bytestream-fifo"
33 * define DYNAMIC in this example for a dynamically allocated fifo.
35 * Otherwise the fifo storage will be a part of the fifo structure.
60 printk(KERN_INFO "byte stream fifo test start\n"); in testfunc()
62 /* put string into the fifo */ in testfunc()
65 /* put values into the fifo */ in testfunc()
70 printk(KERN_INFO "fifo len: %u\n", kfifo_len(&test)); in testfunc()
72 /* get max of 5 bytes from the fifo */ in testfunc()
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| D | inttype-example.c | 17 * This module shows how to create a int type fifo.
20 /* fifo size in elements (ints) */
24 #define PROC_FIFO "int-fifo"
33 * define DYNAMIC in this example for a dynamically allocated fifo.
35 * Otherwise the fifo storage will be a part of the fifo structure.
60 printk(KERN_INFO "int fifo test start\n"); in testfunc()
62 /* put values into the fifo */ in testfunc()
67 printk(KERN_INFO "fifo len: %u\n", kfifo_len(&test)); in testfunc()
69 /* get max of 2 elements from the fifo */ in testfunc()
72 /* and put it back to the end of the fifo */ in testfunc()
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| D | record-example.c | 2 * Sample dynamic sized record fifo implementation
17 * This module shows how to create a variable sized record fifo.
20 /* fifo size in elements (bytes) */
24 #define PROC_FIFO "record-fifo"
33 * define DYNAMIC in this example for a dynamically allocated fifo.
35 * Otherwise the fifo storage will be a part of the fifo structure.
78 printk(KERN_INFO "record fifo test start\n"); in testfunc()
82 /* show the size of the next record in the fifo */ in testfunc()
83 printk(KERN_INFO "fifo peek len: %u\n", kfifo_peek_len(&test)); in testfunc()
91 /* skip first element of the fifo */ in testfunc()
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| /linux-3.3/drivers/char/xilinx_hwicap/ |
| D | fifo_icap.c | 39 #define XHI_WF_OFFSET 0x100 /* Write FIFO */
40 #define XHI_RF_OFFSET 0x104 /* Read FIFO */
44 #define XHI_WFV_OFFSET 0x114 /* Write FIFO Vacancy Register */
45 #define XHI_RFO_OFFSET 0x118 /* Read FIFO Occupancy Register */
66 #define XHI_IPIXR_RFULL_MASK 0x00000008 /* Read FIFO Full */
67 #define XHI_IPIXR_WEMPTY_MASK 0x00000004 /* Write FIFO Empty */
68 #define XHI_IPIXR_RDP_MASK 0x00000002 /* Read FIFO half full */
69 #define XHI_IPIXR_WRP_MASK 0x00000001 /* Write FIFO half full */
74 #define XHI_CR_FIFO_CLR_MASK 0x00000004 /* FIFO Clear Mask */
75 #define XHI_CR_READ_MASK 0x00000002 /* Read from ICAP to FIFO */
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| /linux-3.3/sound/arm/ |
| D | aaci.h | 22 #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */
23 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
44 #define AACI_ALLINTS 0x084 /* all fifo interrupt status */
46 #define AACI_DR1 0x090 /* data read/written fifo 1 */
47 #define AACI_DR2 0x0b0 /* data read/written fifo 2 */
48 #define AACI_DR3 0x0d0 /* data read/written fifo 3 */
49 #define AACI_DR4 0x0f0 /* data read/written fifo 4 */
52 * TX/RX fifo control register (CR). P48
54 #define CR_FEN (1 << 16) /* fifo enable */
77 #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
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| /linux-3.3/sound/soc/tegra/ |
| D | tegra_spdif.h | 89 /* Interrupt when RX user FIFO attention level is reached */
92 /* Interrupt when TX user FIFO attention level is reached */
95 /* Interrupt when RX data FIFO attention level is reached */
98 /* Interrupt when TX data FIFO attention level is reached */
166 * TX User data FIFO busy.
168 * there's data in the TX user FIFO. This bit is deassert when either,
170 * (b) there's no data left in the TX user FIFO.
174 /* TX FIFO Underrun error status */
177 /* RX FIFO Overrun error status */
197 * RX User FIFO Status:
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| /linux-3.3/drivers/spi/ |
| D | spi-mpc512x-psc.c | 39 struct mpc512x_psc_fifo __iomem *fifo; member
139 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; in mpc512x_psc_spi_transfer_rxtx() local
160 * depends on the fifo size. in mpc512x_psc_spi_transfer_rxtx()
162 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); in mpc512x_psc_spi_transfer_rxtx()
168 setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF); in mpc512x_psc_spi_transfer_rxtx()
169 out_8(&fifo->txdata_8, data); in mpc512x_psc_spi_transfer_rxtx()
175 /* interrupt on tx fifo empty */ in mpc512x_psc_spi_transfer_rxtx()
176 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); in mpc512x_psc_spi_transfer_rxtx()
177 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); in mpc512x_psc_spi_transfer_rxtx()
187 /* rx fifo should have count bytes in it */ in mpc512x_psc_spi_transfer_rxtx()
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| /linux-3.3/drivers/gpu/drm/vmwgfx/ |
| D | vmwgfx_fifo.c | 36 const struct vmw_fifo_state *fifo = &dev_priv->fifo; in vmw_fifo_have_3d() local
46 ((fifo->capabilities & in vmw_fifo_have_3d()
79 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) in vmw_fifo_init() argument
86 fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE; in vmw_fifo_init()
87 fifo->static_buffer = vmalloc(fifo->static_buffer_size); in vmw_fifo_init()
88 if (unlikely(fifo->static_buffer == NULL)) in vmw_fifo_init()
91 fifo->dynamic_buffer = NULL; in vmw_fifo_init()
92 fifo->reserved_size = 0; in vmw_fifo_init()
93 fifo->using_bounce_buffer = false; in vmw_fifo_init()
95 mutex_init(&fifo->fifo_mutex); in vmw_fifo_init()
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| /linux-3.3/arch/powerpc/platforms/52xx/ |
| D | mpc52xx_lpbfifo.c | 2 * LocalPlus Bus FIFO driver for the Freescale MPC52xx.
28 MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");
57 /* The MPC5200 has only one fifo, so only need one instance structure */
81 /* While the FIFO can be setup for transfer sizes as large as in mpc52xx_lpbfifo_kick()
82 * 16M-1, the FIFO itself is only 512 bytes deep and it does in mpc52xx_lpbfifo_kick()
83 * not generate interrupts for FIFO full events (only transfer in mpc52xx_lpbfifo_kick()
85 * Bestcomm to drive the FIFO it needs to either be polled, or in mpc52xx_lpbfifo_kick()
86 * transfers need to constrained to the size of the fifo. in mpc52xx_lpbfifo_kick()
93 /* Load the FIFO with data */ in mpc52xx_lpbfifo_kick()
141 * work, just increase the number of bytes the FIFO is in mpc52xx_lpbfifo_kick()
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| /linux-3.3/drivers/memstick/host/ |
| D | r592.h | 22 #define R592_TPC_EXEC_BIG_FIFO (1 << 26) /* If bit 26 is set, large fifo is used (reg 48) */
26 /* Window for small TPC fifo (big endian)*/
28 /* Not used in driver, because large fifo does better job */
32 /* Status register (ms int, small fifo, IO)*/
40 /* Fifo status */
41 #define R592_STATUS_SFIFO_FULL (1 << 20) /* Small Fifo almost full (last chunk is written) */
42 #define R592_STATUS_SFIFO_EMPTY (1 << 21) /* Small Fifo empty */
51 #define R592_STATUS_SFIFO_INPUT (1 << 30) /* Small fifo received data*/
53 #define R592_SFIFO_SIZE 32 /* total size of small fifo is 32 bytes */
54 #define R592_SFIFO_PACKET 8 /* packet size of small fifo */
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| /linux-3.3/arch/powerpc/sysdev/bestcomm/ |
| D | gen_bd.c | 40 u32 fifo; /* (u32*) address of gen_bd's fifo */ member
57 u32 fifo; /* (u32*) address of gen_bd's fifo */ member
77 phys_addr_t fifo; member
89 bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo, in bcom_gen_bd_rx_init() argument
103 priv->fifo = fifo; in bcom_gen_bd_rx_init()
136 var->fifo = (u32) priv->fifo; in bcom_gen_bd_rx_reset()
174 bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo, in bcom_gen_bd_tx_init() argument
188 priv->fifo = fifo; in bcom_gen_bd_tx_init()
220 var->fifo = (u32) priv->fifo; in bcom_gen_bd_tx_reset()
314 * @fifo: physical address of FIFO register
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