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/qemu/include/hw/misc/
H A Dxlnx-zynqmp-crf.h18 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
20 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
22 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
24 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
26 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
28 FIELD(CRF_WPROT, ACTIVE, 0, 1)
30 FIELD(APLL_CTRL, POST_SRC, 24, 3)
31 FIELD(APLL_CTRL, PRE_SRC, 20, 3)
32 FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
33 FIELD(APLL_CTRL, DIV2, 16, 1)
[all …]
H A Dxlnx-versal-cfu.h35 FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
36 FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
37 FIELD(CFU_ISR, SLVERR, 7, 1)
38 FIELD(CFU_ISR, DECOMP_ERROR, 6, 1)
39 FIELD(CFU_ISR, BAD_CFI_PACKET, 5, 1)
40 FIELD(CFU_ISR, AXI_ALIGN_ERROR, 4, 1)
41 FIELD(CFU_ISR, CFI_ROW_ERROR, 3, 1)
42 FIELD(CFU_ISR, CRC32_ERROR, 2, 1)
43 FIELD(CFU_ISR, CRC8_ERROR, 1, 1)
44 FIELD(CFU_ISR, SEU_ENDOFCALIB, 0, 1)
[all …]
H A Dxlnx-versal-crl.h20 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
22 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
24 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
26 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
28 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
30 FIELD(WPROT, ACTIVE, 0, 1)
32 FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
34 FIELD(RPLL_CTRL, POST_SRC, 24, 3)
35 FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
36 FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
[all …]
H A Dxlnx-versal-cframe-reg.h39 FIELD(CRC, CRC, 0, 32)
44 FIELD(FAR0, SEGMENT, 23, 2)
45 FIELD(FAR0, BLOCKTYPE, 20, 3)
46 FIELD(FAR0, FRAME_ADDR, 0, 20)
51 FIELD(FAR_SFR0, BLOCKTYPE, 20, 3)
52 FIELD(FAR_SFR0, FRAME_ADDR, 0, 20)
61 FIELD(FRCNT0, FRCNT, 0, 32)
66 FIELD(CMD0, CMD, 0, 5)
75 FIELD(CTL, PER_FRAME_CRC, 0, 1)
80 FIELD(CFRM_ISR0, READ_BROADCAST_ERROR, 21, 1)
[all …]
H A Dstm32l4x5_rcc_internals.h32 FIELD(CR, PLLSAI2RDY, 29, 1)
33 FIELD(CR, PLLSAI2ON, 28, 1)
34 FIELD(CR, PLLSAI1RDY, 27, 1)
35 FIELD(CR, PLLSAI1ON, 26, 1)
36 FIELD(CR, PLLRDY, 25, 1)
37 FIELD(CR, PLLON, 24, 1)
38 FIELD(CR, CSSON, 19, 1)
39 FIELD(CR, HSEBYP, 18, 1)
40 FIELD(CR, HSERDY, 17, 1)
41 FIELD(CR, HSEON, 16, 1)
[all …]
H A Dxlnx-zynqmp-apu-ctrl.h22 FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
24 FIELD(ISR, INV_APB, 0, 1)
26 FIELD(IMR, INV_APB, 0, 1)
28 FIELD(IEN, INV_APB, 0, 1)
30 FIELD(IDS, INV_APB, 0, 1)
32 FIELD(CONFIG_0, CFGTE, 24, 4)
33 FIELD(CONFIG_0, CFGEND, 16, 4)
34 FIELD(CONFIG_0, VINITHI, 8, 4)
35 FIELD(CONFIG_0, AA64NAA32, 0, 4)
37 FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
[all …]
H A Dxlnx-versal-xramc.h21 FIELD(XRAM_ERR_CTRL, UE_RES, 3, 1)
22 FIELD(XRAM_ERR_CTRL, PWR_ERR_RES, 2, 1)
23 FIELD(XRAM_ERR_CTRL, PZ_ERR_RES, 1, 1)
24 FIELD(XRAM_ERR_CTRL, APB_ERR_RES, 0, 1)
26 FIELD(XRAM_ISR, INV_APB, 0, 1)
28 FIELD(XRAM_IMR, INV_APB, 0, 1)
30 FIELD(XRAM_IEN, INV_APB, 0, 1)
32 FIELD(XRAM_IDS, INV_APB, 0, 1)
34 FIELD(XRAM_ECC_CNTL, FI_MODE, 2, 1)
35 FIELD(XRAM_ECC_CNTL, DET_ONLY, 1, 1)
[all …]
/qemu/hw/intc/
H A Dxlnx-pmu-iomod-intc.c52 FIELD(GPO0, MAGIC_WORD_1, 24, 8)
53 FIELD(GPO0, MAGIC_WORD_2, 16, 8)
54 FIELD(GPO0, FT_INJECT_FAILURE, 13, 3)
55 FIELD(GPO0, DISABLE_RST_FTSM, 12, 1)
56 FIELD(GPO0, RST_FTSM, 11, 1)
57 FIELD(GPO0, CLR_FTSTS, 10, 1)
58 FIELD(GPO0, RST_ON_SLEEP, 9, 1)
59 FIELD(GPO0, DISABLE_TRACE_COMP, 8, 1)
60 FIELD(GPO0, PIT3_PRESCALE, 7, 1)
61 FIELD(GPO0, PIT2_PRESCALE, 5, 2)
[all …]
H A Dxlnx-zynqmp-ipi.c51 FIELD(IPI_TRIG, PL_3, 27, 1)
52 FIELD(IPI_TRIG, PL_2, 26, 1)
53 FIELD(IPI_TRIG, PL_1, 25, 1)
54 FIELD(IPI_TRIG, PL_0, 24, 1)
55 FIELD(IPI_TRIG, PMU_3, 19, 1)
56 FIELD(IPI_TRIG, PMU_2, 18, 1)
57 FIELD(IPI_TRIG, PMU_1, 17, 1)
58 FIELD(IPI_TRIG, PMU_0, 16, 1)
59 FIELD(IPI_TRIG, RPU_1, 9, 1)
60 FIELD(IPI_TRIG, RPU_0, 8, 1)
[all …]
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c41 FIELD(MIO_PIN_0, L3_SEL, 7, 3)
42 FIELD(MIO_PIN_0, L2_SEL, 5, 2)
43 FIELD(MIO_PIN_0, L1_SEL, 3, 2)
44 FIELD(MIO_PIN_0, L0_SEL, 1, 2)
46 FIELD(MIO_PIN_1, L3_SEL, 7, 3)
47 FIELD(MIO_PIN_1, L2_SEL, 5, 2)
48 FIELD(MIO_PIN_1, L1_SEL, 3, 2)
49 FIELD(MIO_PIN_1, L0_SEL, 1, 2)
51 FIELD(MIO_PIN_2, L3_SEL, 7, 3)
52 FIELD(MIO_PIN_2, L2_SEL, 5, 2)
[all …]
/qemu/hw/usb/
H A Dhcd-dwc3.c48 FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4)
49 FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4)
50 FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4)
51 FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4)
52 FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4)
53 FIELD(GSBUSCFG0, DATBIGEND, 11, 1)
54 FIELD(GSBUSCFG0, DESBIGEND, 10, 1)
55 FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2)
56 FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1)
57 FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1)
[all …]
/qemu/include/hw/
H A Dregisterfields.h2 * Register Definition API: field macros
37 /* Define SHIFT, LENGTH and MASK constants for a field within a register */
40 * constants for field BAR in register FOO.
42 #define FIELD(reg, field, shift, length) \ argument
43 enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
44 enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
45 enum { R_ ## reg ## _ ## field ## _MASK = \
48 /* Extract a field from a register */
49 #define FIELD_EX8(storage, reg, field) \ argument
50 extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
[all …]
/qemu/tests/vmstate-static-checker-data/
H A Ddump1.json15 "field": "cur_entry", string
21 "field": "cur_offset", string
27 "field": "cur_offset", string
45 "field": "ehci", string
55 "field": "usbcmd", string
61 "field": "usbsts", string
67 "field": "usbsts_pending", string
73 "field": "usbsts_frindex", string
79 "field": "usbintr", string
85 "field": "frindex", string
[all …]
H A Ddump2.json15 "field": "cur_entry", string
21 "field": "cur_offset", string
27 "field": "cur_offset", string
45 "field": "ehci", string
55 "field": "usbcmd", string
61 "field": "usbsts_pending", string
67 "field": "usbsts_frindex", string
73 "field": "usbintr", string
79 "field": "frindex", string
85 "field": "ctrldssegment", string
[all …]
/qemu/target/loongarch/
H A Dcpu-csr.h19 FIELD(CSR_PRMD, PPLV, 0, 2)
20 FIELD(CSR_PRMD, PIE, 2, 1)
21 FIELD(CSR_PRMD, PWE, 3, 1)
24 FIELD(CSR_EUEN, FPE, 0, 1)
25 FIELD(CSR_EUEN, SXE, 1, 1)
26 FIELD(CSR_EUEN, ASXE, 2, 1)
27 FIELD(CSR_EUEN, BTE, 3, 1)
30 FIELD(CSR_MISC, VA32, 0, 4)
31 FIELD(CSR_MISC, DRDTL, 4, 4)
32 FIELD(CSR_MISC, RPCNTL, 8, 4)
[all …]
H A Dcpu.h50 FIELD(FCSR0, ENABLES, 0, 5)
51 FIELD(FCSR0, RM, 8, 2)
52 FIELD(FCSR0, FLAGS, 16, 5)
53 FIELD(FCSR0, CAUSE, 24, 5)
121 FIELD(CPUCFG0, PRID, 0, 32)
124 FIELD(CPUCFG1, ARCH, 0, 2)
125 FIELD(CPUCFG1, PGMMU, 2, 1)
126 FIELD(CPUCFG1, IOCSR, 3, 1)
127 FIELD(CPUCFG1, PALEN, 4, 8)
128 FIELD(CPUCFG1, VALEN, 12, 8)
[all …]
/qemu/include/qemu/
H A Drcu_queue.h36 #define QLIST_NEXT_RCU(elm, field) (qatomic_rcu_read(&(elm)->field.le_next)) argument
61 #define QLIST_INSERT_AFTER_RCU(listelm, elm, field) do { \ argument
62 (elm)->field.le_next = (listelm)->field.le_next; \
63 (elm)->field.le_prev = &(listelm)->field.le_next; \
64 qatomic_rcu_set(&(listelm)->field.le_next, (elm)); \
65 if ((elm)->field.le_next != NULL) { \
66 (elm)->field.le_next->field.le_prev = \
67 &(elm)->field.le_next; \
77 #define QLIST_INSERT_BEFORE_RCU(listelm, elm, field) do { \ argument
78 (elm)->field.le_prev = (listelm)->field.le_prev; \
[all …]
H A Dqueue.h105 #define QLIST_SWAP(dstlist, srclist, field) do { \ argument
110 (srclist)->lh_first->field.le_prev = &(srclist)->lh_first; \
114 (dstlist)->lh_first->field.le_prev = &(dstlist)->lh_first; \
118 #define QLIST_INSERT_AFTER(listelm, elm, field) do { \ argument
119 if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \
120 (listelm)->field.le_next->field.le_prev = \
121 &(elm)->field.le_next; \
122 (listelm)->field.le_next = (elm); \
123 (elm)->field.le_prev = &(listelm)->field.le_next; \
126 #define QLIST_INSERT_BEFORE(listelm, elm, field) do { \ argument
[all …]
/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c49 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
52 FIELD(MODE_SELECT_REGISTER, ITO, 8, 8)
53 FIELD(MODE_SELECT_REGISTER, ABR, 7, 1)
54 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
55 FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1)
56 FIELD(MODE_SELECT_REGISTER, DAR, 4, 1)
57 FIELD(MODE_SELECT_REGISTER, BRSD, 3, 1)
58 FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
59 FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
[all …]
/qemu/gdb-xml/
H A Di386-32bit.xml13 <field name="" start="22" end="31"/>
14 <field name="ID" start="21" end="21"/>
15 <field name="VIP" start="20" end="20"/>
16 <field name="VIF" start="19" end="19"/>
17 <field name="AC" start="18" end="18"/>
18 <field name="VM" start="17" end="17"/>
19 <field name="RF" start="16" end="16"/>
20 <field name="" start="15" end="15"/>
21 <field name="NT" start="14" end="14"/>
22 <field name="IOPL" start="12" end="13"/>
[all …]
H A Di386-64bit.xml14 <field name="" start="22" end="31"/>
15 <field name="ID" start="21" end="21"/>
16 <field name="VIP" start="20" end="20"/>
17 <field name="VIF" start="19" end="19"/>
18 <field name="AC" start="18" end="18"/>
19 <field name="VM" start="17" end="17"/>
20 <field name="RF" start="16" end="16"/>
21 <field name="" start="15" end="15"/>
22 <field name="NT" start="14" end="14"/>
23 <field name="IOPL" start="12" end="13"/>
[all …]
/qemu/target/arm/
H A Dcpregs.h29 * ARMCPRegInfo type field bits:
154 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
239 * Valid values for ARMCPRegInfo state field, indicating which of
360 FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
361 FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
362 FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
363 FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
364 FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
365 FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
366 FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
[all …]
H A Dcpu.h182 /* See the commentary above the TBFLAG field definitions. */
261 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
264 * semantics as for AArch32, as described in the comments on each field)
992 * Field names match the official register names as defined in the
1002 * field by reading the value from the KVM vCPU.
1479 FIELD(SVCR, SM, 0, 1)
1480 FIELD(SVCR, ZA, 1, 1)
1483 FIELD(SMCR, LEN, 0, 4)
1484 FIELD(SMCR, FA64, 31, 1)
1832 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
[all …]
/qemu/migration/
H A Dvmstate.c30 /* Whether this field should exist for either save or load the VM? */
32 vmstate_field_exists(const VMStateDescription *vmsd, const VMStateField *field, in vmstate_field_exists() argument
37 if (field->field_exists) { in vmstate_field_exists()
39 result = field->field_exists(opaque, version_id); in vmstate_field_exists()
40 trace_vmstate_field_exists(vmsd->name, field->name, field->version_id, in vmstate_field_exists()
44 * Otherwise, we only save/load if field version is same or older. in vmstate_field_exists()
48 result = field->version_id <= version_id; in vmstate_field_exists()
55 * Create a fake nullptr field when there's a NULL pointer detected in the
56 * array of a VMS_ARRAY_OF_POINTER VMSD field. It's needed because we
60 vmsd_create_fake_nullptr_field(const VMStateField *field) in vmsd_create_fake_nullptr_field() argument
[all …]
/qemu/hw/char/
H A Dstm32l4x5_usart.c36 FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */
37 FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */
38 FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
39 FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */
40 FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */
41 FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
42 FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */
43 FIELD(CR1, MME, 13, 1) /* Mute mode enable */
44 FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */
45 FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */
[all …]

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