xref: /linux/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml (revision 4f9786035f9e519db41375818e1d0b5f20da2f10) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arm CoreSight Trace Memory Controller
8
9maintainers:
10  - Mathieu Poirier <mathieu.poirier@linaro.org>
11  - Mike Leach <mike.leach@linaro.org>
12  - Leo Yan <leo.yan@linaro.org>
13  - Suzuki K Poulose <suzuki.poulose@arm.com>
14
15description: |
16  CoreSight components are compliant with the ARM CoreSight architecture
17  specification and can be connected in various topologies to suit a particular
18  SoCs tracing needs. These trace components can generally be classified as
19  sinks, links and sources. Trace data produced by one or more sources flows
20  through the intermediate links connecting the source to the currently selected
21  sink.
22
23  Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
24  FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
25  mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
26
27# Need a custom select here or 'arm,primecell' will match on lots of nodes
28select:
29  properties:
30    compatible:
31      contains:
32        const: arm,coresight-tmc
33  required:
34    - compatible
35
36allOf:
37  - $ref: /schemas/arm/primecell.yaml#
38
39properties:
40  compatible:
41    items:
42      - const: arm,coresight-tmc
43      - const: arm,primecell
44
45  reg:
46    maxItems: 1
47
48  clocks:
49    minItems: 1
50    maxItems: 2
51
52  clock-names:
53    minItems: 1
54    items:
55      - const: apb_pclk
56      - const: atclk
57
58  iommus:
59    maxItems: 1
60
61  power-domains:
62    maxItems: 1
63
64  arm,buffer-size:
65    $ref: /schemas/types.yaml#/definitions/uint32
66    deprecated: true
67    description:
68      Size of contiguous buffer space for TMC ETR (embedded trace router). The
69      buffer size can be configured dynamically via buffer_size property in
70      sysfs instead.
71
72  arm,scatter-gather:
73    type: boolean
74    description:
75      Indicates that the TMC-ETR can safely use the SG mode on this system.
76
77  arm,max-burst-size:
78    description:
79      The maximum burst size initiated by TMC on the AXI master interface. The
80      burst size can be in the range [0..15], the setting supports one data
81      transfer per burst up to a maximum of 16 data transfers per burst.
82    $ref: /schemas/types.yaml#/definitions/uint32
83    maximum: 15
84
85  in-ports:
86    $ref: /schemas/graph.yaml#/properties/ports
87    additionalProperties: false
88
89    properties:
90      port:
91        description: Input connection from the CoreSight Trace bus.
92        $ref: /schemas/graph.yaml#/properties/port
93
94  out-ports:
95    $ref: /schemas/graph.yaml#/properties/ports
96    additionalProperties: false
97
98    properties:
99      port:
100        description: AXI or ATB Master output connection. Used for ETR
101          and ETF configurations.
102        $ref: /schemas/graph.yaml#/properties/port
103
104  memory-region:
105    items:
106      - description: Reserved trace buffer memory for ETR and ETF sinks.
107          For ETR, this reserved memory region is used for trace data capture.
108          Same region is used for trace data retention as well after a panic
109          or watchdog reset.
110          This reserved memory region is used as trace buffer or used for trace
111          data retention only if specifically selected by the user in sysfs
112          interface.
113          The default memory usage models for ETR in sysfs/perf modes are
114          otherwise unaltered.
115
116          For ETF, this reserved memory region is used by default for
117          retention of trace data synced from internal SRAM after a panic
118          or watchdog reset.
119      - description: Reserved meta data memory. Used for ETR and ETF sinks
120          for storing metadata.
121
122  memory-region-names:
123    items:
124      - const: tracedata
125      - const: metadata
126
127required:
128  - compatible
129  - reg
130  - clocks
131  - clock-names
132  - in-ports
133
134unevaluatedProperties: false
135
136examples:
137  - |
138    etr@20070000 {
139        compatible = "arm,coresight-tmc", "arm,primecell";
140        reg = <0x20070000 0x1000>;
141        memory-region = <&etr_trace_mem_reserved>,
142                       <&etr_mdata_mem_reserved>;
143        memory-region-names = "tracedata", "metadata";
144
145        clocks = <&oscclk6a>;
146        clock-names = "apb_pclk";
147        in-ports {
148            port {
149                etr_in_port: endpoint {
150                    remote-endpoint = <&replicator2_out_port0>;
151                };
152            };
153        };
154
155        out-ports {
156            port {
157                etr_out_port: endpoint {
158                    remote-endpoint = <&catu_in_port>;
159                };
160            };
161        };
162    };
163...
164