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/linux-6.8/Documentation/devicetree/bindings/clock/
Dmediatek,ethsys.yaml4 $id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
7 title: Mediatek ethsys controller
20 - mediatek,mt2701-ethsys
21 - mediatek,mt7622-ethsys
22 - mediatek,mt7629-ethsys
23 - mediatek,mt7981-ethsys
24 - mediatek,mt7986-ethsys
25 - mediatek,mt7988-ethsys
28 - const: mediatek,mt7623-ethsys
29 - const: mediatek,mt2701-ethsys
[all …]
/linux-6.8/Documentation/devicetree/bindings/net/
Dmediatek,net.yaml52 mediatek,ethsys:
413 - mediatek,ethsys
435 <&ethsys CLK_ETH_ESW_EN>,
436 <&ethsys CLK_ETH_GP0_EN>,
437 <&ethsys CLK_ETH_GP1_EN>,
438 <&ethsys CLK_ETH_GP2_EN>,
450 mediatek,ethsys = <&ethsys>;
515 clocks = <&ethsys CLK_ETH_FE_EN>,
516 <&ethsys CLK_ETH_GP2_EN>,
517 <&ethsys CLK_ETH_GP1_EN>,
[all …]
/linux-6.8/arch/arm/boot/dts/mediatek/
Dmt7629.dtsi430 ethsys: syscon@1b000000 { label
431 compatible = "mediatek,mt7629-ethsys", "syscon";
445 <&ethsys CLK_ETH_ESW_EN>,
446 <&ethsys CLK_ETH_GP0_EN>,
447 <&ethsys CLK_ETH_GP1_EN>,
448 <&ethsys CLK_ETH_GP2_EN>,
449 <&ethsys CLK_ETH_FE_EN>,
471 mediatek,ethsys = <&ethsys>;
Dmt2701.dtsi720 ethsys: syscon@1b000000 { label
721 compatible = "mediatek,mt2701-ethsys", "syscon";
734 <&ethsys CLK_ETHSYS_ESW>,
735 <&ethsys CLK_ETHSYS_GP1>,
736 <&ethsys CLK_ETHSYS_GP2>,
739 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
740 <&ethsys MT2701_ETHSYS_GMAC_RST>,
741 <&ethsys MT2701_ETHSYS_PPE_RST>;
744 mediatek,ethsys = <&ethsys>;
Dmt7623.dtsi940 ethsys: syscon@1b000000 { label
941 compatible = "mediatek,mt7623-ethsys",
942 "mediatek,mt2701-ethsys",
953 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
968 <&ethsys CLK_ETHSYS_ESW>,
969 <&ethsys CLK_ETHSYS_GP1>,
970 <&ethsys CLK_ETHSYS_GP2>,
973 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
974 <&ethsys MT2701_ETHSYS_GMAC_RST>,
975 <&ethsys MT2701_ETHSYS_PPE_RST>;
[all …]
Dmt7623a.dtsi54 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
/linux-6.8/drivers/net/ethernet/mediatek/
Dmtk_eth_path.c144 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac1_gmac2_to_sgmii_rgmii()
159 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac1_gmac2_to_sgmii_rgmii()
173 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac12_to_gephy_sgmii()
190 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac12_to_gephy_sgmii()
Dmtk_eth_soc.c476 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
613 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
616 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
627 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
629 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
673 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
3538 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3543 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3667 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3691 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
[all …]
/linux-6.8/arch/arm64/boot/dts/mediatek/
Dmt7986a.dtsi500 ethsys: syscon@15000000 { label
503 compatible = "mediatek,mt7986-ethsys",
557 clocks = <&ethsys CLK_ETH_FE_EN>,
558 <&ethsys CLK_ETH_GP2_EN>,
559 <&ethsys CLK_ETH_GP1_EN>,
560 <&ethsys CLK_ETH_WOCPU1_EN>,
561 <&ethsys CLK_ETH_WOCPU0_EN>,
582 mediatek,ethsys = <&ethsys>;
Dmt7622.dtsi929 ethsys: syscon@1b000000 { label
930 compatible = "mediatek,mt7622-ethsys",
941 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
977 <&ethsys CLK_ETH_ESW_EN>,
978 <&ethsys CLK_ETH_GP0_EN>,
979 <&ethsys CLK_ETH_GP1_EN>,
980 <&ethsys CLK_ETH_GP2_EN>,
992 mediatek,ethsys = <&ethsys>;
/linux-6.8/drivers/clk/mediatek/
DKconfig54 bool "Clock driver for MediaTek MT2701 ethsys"
57 This driver supports MediaTek MT2701 ethsys clocks.
349 tristate "Clock driver for MediaTek MT7622 ETHSYS"
379 bool "Clock driver for MediaTek MT7629 ETHSYS"
402 tristate "Clock driver for MediaTek MT7981 ETHSYS"
419 tristate "Clock driver for MediaTek MT7986 ETHSYS"
Dclk-mt2701-eth.c49 { .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
Dclk-mt7622-eth.c74 { .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
Dclk-mt7986-eth.c82 { .compatible = "mediatek,mt7986-ethsys", .data = &eth_desc },
Dclk-mt7981-eth.c101 { .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },
Dclk-mt7629-eth.c122 .compatible = "mediatek,mt7629-ethsys",
Dclk-mt7988-eth.c131 { .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
/linux-6.8/Documentation/devicetree/bindings/crypto/
Dmediatek-crypto.txt22 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
/linux-6.8/include/dt-bindings/reset/
Dmt7986-resets.h46 /* ETHSYS Subsystem resets */
Dmt2701-resets.h75 /* ETHSYS resets */
Dmt7622-reset.h76 /* ETHSYS Subsystem resets */
/linux-6.8/Documentation/devicetree/bindings/dma/
Dmtk-hsdma.txt27 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
/linux-6.8/include/dt-bindings/clock/
Dmt7986-clk.h161 /* ETHSYS */
Dmt7629-clk.h188 /* ETHSYS */
Dmediatek,mt7981-clk.h209 /* ETHSYS */

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