Searched +full:ethernet +full:- +full:phy (Results 1 – 25 of 1074) sorted by relevance
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/linux-6.8/arch/powerpc/boot/dts/fsl/ |
D | t4240qds.dts | 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 35 /include/ "t4240si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "cfi-flash"; 94 bank-width = <2>; 95 device-width = <1>; [all …]
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D | t2081qds.dts | 4 * Copyright 2013 - 2015 Freescale Semiconductor Inc. 35 /include/ "t208xsi-pre.dtsi" 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 57 ethernet@e0000 { 58 phy-handle = <&phy_sgmii_s7_1c>; 59 phy-connection-type = "sgmii"; 62 ethernet@e2000 { 63 phy-handle = <&phy_sgmii_s7_1d>; [all …]
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D | t2080qds.dts | 4 * Copyright 2013 - 2015 Freescale Semiconductor Inc. 35 /include/ "t208xsi-pre.dtsi" 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 65 ethernet@e0000 { 66 phy-handle = <&phy_sgmii_s3_1e>; 67 phy-connection-type = "xgmii"; 70 ethernet@e2000 { 71 phy-handle = <&phy_sgmii_s3_1f>; [all …]
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D | t4240rdb.dts | 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 35 /include/ "t4240si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "cfi-flash"; 67 bank-width = <2>; 68 device-width = <1>; [all …]
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D | t2080rdb.dts | 2 * T2080PCIe-RDB Board Device Tree Source 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 35 /include/ "t208xsi-pre.dtsi" 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 59 ethernet@e0000 { 60 phy-handle = <&xg_aq1202_phy3>; 61 phy-connection-type = "xgmii"; 64 ethernet@e2000 { [all …]
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D | p5040ds.dts | 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 35 /include/ "p5040si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 74 reserved-memory { 75 #address-cells = <2>; 76 #size-cells = <2>; 79 bman_fbpr: bman-fbpr { 83 qman_fqd: qman-fqd { [all …]
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D | p4080ds.dts | 4 * Copyright 2009 - 2015 Freescale Semiconductor Inc. 35 /include/ "p4080si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 67 bman_fbpr: bman-fbpr { 71 qman_fqd: qman-fqd { [all …]
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D | t1040rdb.dts | 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 35 /include/ "t104xsi-pre.dtsi" 48 ethernet@e0000 { 49 fixed-link = <0 1 1000 0 0>; 50 phy-connection-type = "sgmii"; 53 ethernet@e2000 { 54 fixed-link = <1 1 1000 0 0>; 55 phy-connection-type = "sgmii"; 58 ethernet@e4000 { 59 phy-handle = <&phy_sgmii_2>; [all …]
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/linux-6.8/arch/arm64/boot/dts/freescale/ |
D | fsl-ls2088a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 12 /dts-v1/; 14 #include "fsl-ls2088a.dtsi" 15 #include "fsl-ls208xa-rdb.dtsi" 19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; 22 stdout-path = "serial1:115200n8"; 27 phy-handle = <&mdio1_phy1>; 28 phy-connection-type = "10gbase-r"; 32 phy-handle = <&mdio1_phy2>; 33 phy-connection-type = "10gbase-r"; [all …]
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D | tqmls104xa-mbls10xxa-fman.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 3 * Copyright (c) 2019,2023 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 10 #include <dt-bindings/net/ti-dp83867.h> 21 phy-handle = <&rgmii_phy1>; 22 phy-connection-type = "rgmii"; 23 phy-mode = "rgmii-id"; 28 phy-handle = <&rgmii_phy2>; 29 phy-connection-type = "rgmii"; 30 phy-mode = "rgmii-id"; [all …]
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D | fsl-lx2160a-bluebox3.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 // Copyright 2020-2021 NXP 7 /dts-v1/; 9 #include "fsl-lx2160a.dtsi" 13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a"; 23 stdout-path = "serial0:115200n8"; 26 sb_3v3: regulator-sb3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "MC34717-3.3VSB"; 29 regulator-min-microvolt = <3300000>; [all …]
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D | tqmls1088a-mbls10xxa-mc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 3 * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 10 #include <dt-bindings/net/ti-dp83867.h> 15 i2c-bus = <&sfp1_i2c>; 16 mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>; 17 los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>; 18 tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>; 19 tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>; 24 i2c-bus = <&sfp2_i2c>; [all …]
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D | fsl-ls1028a-qds-13bb.dtso | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Copyright 2019-2021 NXP 8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C. 9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2. 12 /dts-v1/; 16 #address-cells = <1>; 17 #size-cells = <0>; 19 slot1_sgmii: ethernet-phy@2 { 22 compatible = "ethernet-phy-ieee802.3-c45"; 27 phy-handle = <&slot1_sgmii>; [all …]
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D | fsl-ls1043a-qds.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018-2021 NXP 11 /dts-v1/; 12 #include "fsl-ls1043a.dtsi" 16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; 27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1; 28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1; 29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1; [all …]
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/linux-6.8/Documentation/devicetree/bindings/net/dsa/ |
D | marvell,mv88e6xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andrew Lunn <andrew@lunn.ch> 22 - enum: 23 - marvell,mv88e6085 24 - marvell,mv88e6190 25 - marvell,mv88e6250 43 - items: 44 - const: marvell,turris-mox-mv88e6085 [all …]
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/linux-6.8/drivers/net/phy/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # PHY Layer Configuration 12 PHYlink models the link between the PHY and MAC, allowing fixed 17 tristate "PHY Device support and infrastructure" 22 Ethernet controllers are usually attached to PHY 24 managing PHY devices. 35 Adds support for a set of LED trigger events per-PHY. Link 38 supported by the PHY and also a one common "link" trigger as a 39 logical-or of all the link speed ones. 41 <mii bus id>:<phy>:<speed> [all …]
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/linux-6.8/arch/arm64/boot/dts/microchip/ |
D | sparx5_pcb135_board.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 10 gpio-restart { 11 compatible = "gpio-restart"; 17 compatible = "gpio-leds"; 21 default-state = "off"; 26 default-state = "off"; 31 default-state = "off"; 36 default-state = "off"; 41 default-state = "off"; [all …]
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/linux-6.8/Documentation/devicetree/bindings/net/ |
D | marvell,aquantia.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Marvell Aquantia Ethernet PHY 10 - Christian Marangi <ansuelsmth@gmail.com> 13 Marvell Aquantia Ethernet PHY require a firmware to be loaded to actually 17 - Attached SPI flash directly to the PHY with the firmware. The PHY 19 - Read from a dedicated partition on system NAND declared in an 20 NVMEM cell, and loaded to the PHY using its mailbox interface. 21 - Manually provided firmware loaded from a file in the filesystem. [all …]
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D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Ethernet PHY Common Properties 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 14 # The dt-schema tools will generate a select statement first by using 21 pattern: "^ethernet-phy(@[a-f0-9]+)?$" [all …]
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D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: AXI 1G/2.5G Ethernet Subsystem 10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core 11 provides connectivity to an external ethernet PHY supporting different 22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> 27 - xlnx,axi-ethernet-1.00.a 28 - xlnx,axi-ethernet-1.01.a [all …]
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D | hisilicon-hip04-net.txt | 1 Hisilicon hip04 Ethernet Controller 3 * Ethernet controller node 6 - compatible: should be "hisilicon,hip04-mac". 7 - reg: address and length of the register set for the device. 8 - interrupts: interrupt for the device. 9 - port-handle: <phandle port channel> 14 - phy-mode: see ethernet.txt [1]. 17 - phy-handle: see ethernet.txt [1]. 19 [1] Documentation/devicetree/bindings/net/ethernet.txt 22 * Ethernet ppe node: [all …]
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/linux-6.8/arch/arm/boot/dts/marvell/ |
D | armada-385-clearfog-gtr-l8.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 #include "armada-385-clearfog-gtr.dtsi" 10 switch0: ethernet-switch@4 { 13 pinctrl-names = "default"; 14 pinctrl-0 = <&cf_gtr_switch_reset_pins>; 15 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; 17 ethernet-ports { 18 #address-cells = <1>; 19 #size-cells = <0>; 21 ethernet-port@1 { [all …]
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D | armada-381-netgear-gs110emx.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 4 /dts-v1/; 5 #include "armada-385.dtsi" 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/input.h> 14 /* So that mvebu u-boot can update the MAC addresses */ 19 stdout-path = "serial0:115200n8"; 22 gpio-keys { 23 compatible = "gpio-keys"; 24 pinctrl-0 = <&front_button_pins>; [all …]
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/linux-6.8/arch/arm64/boot/dts/marvell/ |
D | armada-3720-turris-mox.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 9 #include <dt-bindings/bus/moxtet.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/input/input.h> 12 #include "armada-372x.dtsi" 16 compatible = "cznic,turris-mox", "marvell,armada3720", 28 stdout-path = "serial0:115200n8"; 37 compatible = "gpio-leds"; 41 linux,default-trigger = "default-on"; [all …]
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D | cn9130-crb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 8 #include <dt-bindings/gpio/gpio.h> 12 stdout-path = "serial0:115200n8"; 30 compatible = "regulator-gpio"; 31 regulator-name = "ap0_mmc_vccq"; 32 regulator-min-microvolt = <1800000>; 33 regulator-max-microvolt = <3300000>; 40 compatible = "regulator-fixed"; 41 regulator-name = "cp0-xhci1-vbus"; 42 regulator-min-microvolt = <5000000>; [all …]
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