| /linux-5.10/drivers/memory/tegra/ |
| D | tegra210-emc-core.c | 21 #include "tegra210-emc.h"
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
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| D | tegra30-emc.c | 5 * Based on downstream driver from NVIDIA and tegra124-emc.c
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
377 struct tegra_emc *emc = data; in tegra_emc_isr() local
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
387 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
391 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
396 static struct emc_timing *emc_find_timing(struct tegra_emc *emc, in emc_find_timing() argument
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| D | tegra186-emc.c | 38 * to control the EMC frequency. The top-level directory can be found here:
40 * /sys/kernel/debug/emc
45 * EMC frequencies.
49 * configured EMC frequency, this will cause the frequency to be
54 * the value is lower than the currently configured EMC frequency, this
59 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, in tegra186_emc_validate_rate() argument
64 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
65 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
74 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show() local
78 for (i = 0; i < emc->num_dvfs; i++) { in tegra186_emc_debug_available_rates_show()
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| D | tegra20-emc.c | 163 struct tegra_emc *emc = data; in tegra_emc_isr() local
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
182 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
189 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
190 timing = &emc->timings[i]; in tegra_emc_find_timing()
196 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
203 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
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| D | tegra124-emc.c | 21 #include <soc/tegra/emc.h>
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
512 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
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| D | tegra210-emc-cc-r21021.c | 14 #include "tegra210-emc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \
116 static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) in update_clock_tree_delay() argument
119 struct tegra210_emc_timing *last = emc->last; in update_clock_tree_delay()
120 struct tegra210_emc_timing *next = emc->next; in update_clock_tree_delay()
134 value = tegra210_emc_mrr_read(emc, 2, 19); in update_clock_tree_delay()
136 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
145 value = tegra210_emc_mrr_read(emc, 2, 18); in update_clock_tree_delay()
147 for (i = 0; i < emc->num_channels; i++) { in update_clock_tree_delay()
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| D | tegra210-emc-table.c | 8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
35 if (emc->derated) { in tegra210_emc_table_device_init()
36 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init()
40 if (emc->nominal) { in tegra210_emc_table_device_init()
41 if (count != emc->num_timings) { in tegra210_emc_table_device_init()
43 count, emc->num_timings); in tegra210_emc_table_device_init()
48 emc->derated = timings; in tegra210_emc_table_device_init()
50 emc->num_timings = count; in tegra210_emc_table_device_init()
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| D | Makefile | 13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
14 obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
15 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
16 obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
17 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
18 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o
19 obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra186-emc.o
21 tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
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| D | Kconfig | 15 This driver is for the External Memory Controller (EMC) found on
16 Tegra20 chips. The EMC controls the external DRAM on the board.
25 This driver is for the External Memory Controller (EMC) found on
26 Tegra30 chips. The EMC controls the external DRAM on the board.
35 This driver is for the External Memory Controller (EMC) found on
36 Tegra124 chips. The EMC controls the external DRAM on the board.
49 This driver is for the External Memory Controller (EMC) found on
50 Tegra210 chips. The EMC controls the external DRAM on the board.
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| D | tegra210-emc.h | 891 /* nominal EMC frequency table */
893 /* derated EMC frequency table */
939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
940 u32 (*periodic_compensation)(struct tegra210_emc *emc);
943 static inline void emc_writel(struct tegra210_emc *emc, u32 value, in emc_writel() argument
946 writel_relaxed(value, emc->regs + offset); in emc_writel()
949 static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) in emc_readl() argument
951 return readl_relaxed(emc->regs + offset); in emc_readl()
954 static inline void emc_channel_writel(struct tegra210_emc *emc, in emc_channel_writel() argument
958 writel_relaxed(value, emc->channel[channel] + offset); in emc_channel_writel()
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| /linux-5.10/arch/arm/boot/dts/ |
| D | tegra124-nyan-blaze-emc.dtsi | 4 emc-timings-1 {
11 clock-names = "emc-parent";
17 clock-names = "emc-parent";
23 clock-names = "emc-parent";
29 clock-names = "emc-parent";
35 clock-names = "emc-parent";
41 clock-names = "emc-parent";
47 clock-names = "emc-parent";
53 clock-names = "emc-parent";
60 clock-names = "emc-parent";
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| D | tegra124-apalis-emc.dtsi | 9 emc-timings-1 {
16 clock-names = "emc-parent";
22 clock-names = "emc-parent";
28 clock-names = "emc-parent";
34 clock-names = "emc-parent";
40 clock-names = "emc-parent";
46 clock-names = "emc-parent";
52 clock-names = "emc-parent";
58 clock-names = "emc-parent";
64 clock-names = "emc-parent";
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| D | tegra124-jetson-tk1-emc.dtsi | 4 emc-timings-3 {
11 clock-names = "emc-parent";
17 clock-names = "emc-parent";
23 clock-names = "emc-parent";
29 clock-names = "emc-parent";
35 clock-names = "emc-parent";
41 clock-names = "emc-parent";
47 clock-names = "emc-parent";
53 clock-names = "emc-parent";
59 clock-names = "emc-parent";
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| D | tegra124-nyan-big-emc.dtsi | 8 emc-timings-1 {
15 clock-names = "emc-parent";
21 clock-names = "emc-parent";
27 clock-names = "emc-parent";
33 clock-names = "emc-parent";
39 clock-names = "emc-parent";
45 clock-names = "emc-parent";
51 clock-names = "emc-parent";
57 clock-names = "emc-parent";
63 clock-names = "emc-parent";
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| D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 {
159 emc-timings-1 {
315 emc-timings-0 {
321 nvidia,emc-auto-cal-interval = <0x001fffff>;
322 nvidia,emc-mode-1 = <0x80100003>;
323 nvidia,emc-mode-2 = <0x80200008>;
324 nvidia,emc-mode-reset = <0x80001221>;
325 nvidia,emc-zcal-cnt-long = <0x00000040>;
326 nvidia,emc-cfg-dyn-self-ref;
327 nvidia,emc-cfg-periodic-qrst;
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| D | tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
22 nvidia,emc-cfg-periodic-qrst;
24 nvidia,emc-configuration = <
118 emc-timings-1 {
122 nvidia,emc-auto-cal-interval = <0x001fffff>;
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| D | tegra20-acer-a500-picasso.dts | 1064 emc-tables@0 {
1070 emc-table@25000 {
1072 compatible = "nvidia,tegra20-emc-table";
1074 nvidia,emc-registers = <0x00000002 0x00000006
1088 emc-table@50000 {
1090 compatible = "nvidia,tegra20-emc-table";
1092 nvidia,emc-registers = <0x00000003 0x00000007
1106 emc-table@75000 {
1108 compatible = "nvidia,tegra20-emc-table";
1110 nvidia,emc-registers = <0x00000005 0x0000000a
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| /linux-5.10/drivers/clk/tegra/ |
| D | clk-tegra20-emc.c | 3 * Based on drivers/clk/tegra/clk-emc.c
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
56 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_recalc_rate() local
59 val = readl_relaxed(emc->reg); in emc_recalc_rate()
67 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_get_parent() local
69 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; in emc_get_parent()
74 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_set_parent() local
77 val = readl_relaxed(emc->reg); in emc_set_parent()
83 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter) in emc_set_parent()
88 if (emc->mc_same_freq) in emc_set_parent()
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| D | clk-tegra210-emc.c | 53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_recalc_rate()
92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_round_rate() local
93 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_round_rate()
107 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, in tegra210_clk_emc_find_parent() argument
110 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); in tegra210_clk_emc_find_parent()
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
30 - const: emc
38 "^emc-timings-[0-9]+$":
57 nvidia,emc-auto-cal-config:
63 nvidia,emc-auto-cal-config2:
69 nvidia,emc-auto-cal-config3:
75 nvidia,emc-auto-cal-interval:
82 nvidia,emc-bgbias-ctl0:
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| D | nvidia,tegra20-emc.txt | 4 - name : Should be emc
7 - compatible : Should contain "nvidia,tegra20-emc".
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
23 compatible = "nvidia,tegra20-emc";
32 If the emc node has the nvidia,use-ram-code property present, then the
33 next level of nodes below the emc table are used to specify which settings
36 If the emc node lacks the nvidia,use-ram-code property, this level is omitted
37 and the tables are stored directly under the emc node (see below).
41 - name : Should be emc-tables
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| D | nvidia,tegra30-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
40 "^emc-timings-[0-9]+$":
58 nvidia,emc-auto-cal-interval:
65 nvidia,emc-mode-1:
70 nvidia,emc-mode-2:
75 nvidia,emc-mode-reset:
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| D | nvidia,tegra210-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra210-emc
30 - const: emc
34 - description: EMC general interrupt
39 phandle to a reserved memory region describing the table of EMC
66 emc_table: emc-table@83400000 {
67 compatible = "nvidia,tegra210-emc-table";
73 compatible = "nvidia,tegra210-emc";
78 clock-names = "emc";
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| /linux-5.10/drivers/pinctrl/ |
| D | pinctrl-lpc18xx.c | 140 [FUNC_EMC] = "emc",
240 LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
241 LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
242 LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
243 LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
244 LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
245 LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
246 LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
247 LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
248 LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-car.txt | 23 - nvidia,external-memory-controller : phandle of the EMC driver.
25 The node should contain a "emc-timings" subnode for each supported RAM type (see
28 Required properties for "emc-timings" nodes :
32 Each "emc-timings" node should contain a "timing" subnode for every supported
33 EMC clock rate.
39 parent of the EMC clock should be running at this timing.
43 - emc-parent : the clock that should be the parent of the EMC clock at this
54 nvidia,external-memory-controller = <&emc>;
90 emc-timings-3 {
97 clock-names = "emc-parent";
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