| /linux-5.10/Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
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| /linux-5.10/drivers/mtd/nand/raw/ |
| D | mtk_ecc.c | 3 * MTK ECC controller driver.
67 /* ecc strength that each IP supports */
118 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
121 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
125 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
135 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
138 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
141 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
142 if (dec & ecc->sectors) { in mtk_ecc_irq()
147 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); in mtk_ecc_irq()
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| D | omap2.c | 122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
170 /* fields specific for BCHx_HW ECC scheme */
718 * gen_true_ecc - This function will generate true ECC value
719 * @ecc_buf: buffer to store ecc code
721 * This generated true ECC value can be used when correcting
739 * @ecc_data1: ecc code from nand spare area
740 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
743 * This function compares two ECC's and indicates if there is an error.
819 * ECC values are equal in omap_compare_ecc()
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| D | nand_micron.c | 15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
66 struct micron_on_die_ecc ecc; member
127 .ecc = micron_nand_on_die_4_ooblayout_ecc,
140 oobregion->offset = mtd->oobsize - chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
141 oobregion->length = chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
156 oobregion->length = mtd->oobsize - chip->ecc.total - 2; in micron_nand_on_die_8_ooblayout_free()
162 .ecc = micron_nand_on_die_8_ooblayout_ecc,
172 if (micron->ecc.forced) in micron_nand_on_die_ecc_setup()
175 if (micron->ecc.enabled == enable) in micron_nand_on_die_ecc_setup()
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| D | nand_bch.c | 3 * This file provides ECC correction for more than 1 bit per block of data,
23 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
32 * nand_bch_calculate_ecc - [NAND Interface] Calculate ECC for data block
35 * @code: output buffer with ECC
40 struct nand_bch_control *nbc = chip->ecc.priv; in nand_bch_calculate_ecc()
43 memset(code, 0, chip->ecc.bytes); in nand_bch_calculate_ecc()
44 bch_encode(nbc->bch, buf, chip->ecc.size, code); in nand_bch_calculate_ecc()
47 for (i = 0; i < chip->ecc.bytes; i++) in nand_bch_calculate_ecc()
58 * @read_ecc: ECC from the chip
59 * @calc_ecc: the ECC calculated from raw data
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| D | sunxi_nand.c | 172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
174 * @mode: the sunxi ECC mode field deduced from ECC requirements
593 bool ecc) in sunxi_nfc_randomizer_state() argument
602 if (ecc) { in sunxi_nfc_randomizer_state()
613 bool ecc) in sunxi_nfc_randomizer_config() argument
623 state = sunxi_nfc_randomizer_state(nand, page, ecc); in sunxi_nfc_randomizer_config()
660 bool ecc, int page) in sunxi_nfc_randomizer_write_buf() argument
662 sunxi_nfc_randomizer_config(nand, page, ecc); in sunxi_nfc_randomizer_write_buf()
669 int len, bool ecc, int page) in sunxi_nfc_randomizer_read_buf() argument
671 sunxi_nfc_randomizer_config(nand, page, ecc); in sunxi_nfc_randomizer_read_buf()
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| D | nand_base.c | 22 * if we have HW ECC support.
262 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
430 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
432 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
2495 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2499 * @ecc: ECC buffer
2500 * @ecclen: ECC length
2505 * Check if a data buffer and its associated ECC and OOB data contains only
2512 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
2513 * different from the NAND page size. When fixing bitflips, ECC engines will
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| D | davinci_nand.c | 33 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
85 * 1-bit hardware ECC ... context maintained for each core chipselect
104 /* Reset ECC hardware */ in nand_davinci_hwctl_1bit()
109 /* Restart ECC hardware */ in nand_davinci_hwctl_1bit()
118 * Read hardware ECC value and pack into three bytes
126 /* invert so that erased block ecc is correct */ in nand_davinci_calculate_1bit()
147 if ((diff >> (12 + 3)) < chip->ecc.size) { in nand_davinci_correct_1bit()
154 /* Single bit ECC error in the ECC itself, in nand_davinci_correct_1bit()
169 * 4-bit hardware ECC ... context maintained over entire AEMIF
174 * Also, and specific to this hardware, it ECC-protects the "prepad"
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| D | qcom_nandc.c | 163 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
177 /* ECC modes supported by the controller */
416 * of a page, consisting of all data, ecc, spare
419 * by ECC
420 * @use_ecc: request the controller to use ECC for the
422 * @bch_enabled: flag to tell whether BCH ECC mode is used
423 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
431 * ecc/non-ecc mode for the current nand flash
460 * @ecc_modes - ecc mode for NAND
1392 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_erase_write_errors() local
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| D | fsmc_nand.c | 163 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_ecc()
177 if (section >= chip->ecc.steps) in fsmc_ecc1_ooblayout_free()
182 if (section < chip->ecc.steps - 1) in fsmc_ecc1_ooblayout_free()
191 .ecc = fsmc_ecc1_ooblayout_ecc,
196 * ECC placement definitions in oobfree type format.
197 * There are 13 bytes of ecc for every 512 byte block and it has to be read
206 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_ecc()
209 oobregion->length = chip->ecc.bytes; in fsmc_ecc4_ooblayout_ecc()
224 if (section >= chip->ecc.steps) in fsmc_ecc4_ooblayout_free()
229 if (section < chip->ecc.steps - 1) in fsmc_ecc4_ooblayout_free()
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| D | lpc32xx_slc.c | 58 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
65 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
66 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
110 /* ECC line party fetch macro */
115 * DMA requires storage space for the DMA local buffer and the hardware ECC
122 /* Number of bytes used for ECC stored in NAND per 256 bytes */
136 * NAND ECC Layout for small page NAND devices
169 .ecc = lpc32xx_ooblayout_ecc,
231 * DMA and CPU addresses of ECC work area and data buffer
327 * Prepares SLC for transfers with H/W ECC enabled
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| D | nand_toshiba.c | 17 /* ECC Status Read Command for BENAND */
20 /* ECC Status Mask for BENAND */
26 /* Max ECC Steps for BENAND */
40 NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0), in toshiba_nand_benand_read_eccstatus_op()
62 for (i = 0; i < chip->ecc.steps; i++) { in toshiba_nand_benand_eccstatus()
128 * The calculated ECC bytes are stored into other isolated in toshiba_nand_benand_init()
130 * This is why chip->ecc.bytes = 0. in toshiba_nand_benand_init()
132 chip->ecc.bytes = 0; in toshiba_nand_benand_init()
133 chip->ecc.size = 512; in toshiba_nand_benand_init()
134 chip->ecc.strength = 8; in toshiba_nand_benand_init()
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| /linux-5.10/drivers/mtd/nand/raw/ingenic/ |
| D | ingenic_ecc.c | 3 * JZ47xx ECC common code
18 * ingenic_ecc_calculate() - calculate ECC for a data buffer
19 * @ecc: ECC device.
20 * @params: ECC parameters.
22 * @ecc_code: output buffer with ECC.
24 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
27 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
31 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
36 * @ecc: ECC device.
37 * @params: ECC parameters.
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| D | ingenic_nand_drv.c | 44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
95 oobregion->length = mtd->oobsize - ecc->total - 12; in qi_lb60_ooblayout_free()
96 oobregion->offset = 12 + ecc->total; in qi_lb60_ooblayout_free()
102 .ecc = qi_lb60_ooblayout_ecc,
110 struct nand_ecc_ctrl *ecc = &chip->ecc; in jz4725b_ooblayout_ecc() local
112 if (section || !ecc->total) in jz4725b_ooblayout_ecc()
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| D | jz4740_ecc.c | 3 * JZ4740 ECC controller driver
45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
52 /* Initialize and enable ECC hardware */ in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
57 if (calc_ecc) /* calculate ECC from data */ in jz4740_ecc_reset()
59 else /* correct data from ECC */ in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
65 static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, in jz4740_ecc_calculate() argument
73 jz4740_ecc_reset(ecc, true); in jz4740_ecc_calculate()
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| D | ingenic_ecc.h | 17 * struct ingenic_ecc_params - ECC parameters
18 * @size: data bytes per ECC step.
19 * @bytes: ECC bytes per step.
20 * @strength: number of correctable bits per ECC step.
29 int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
32 int ingenic_ecc_correct(struct ingenic_ecc *ecc,
36 void ingenic_ecc_release(struct ingenic_ecc *ecc);
39 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
46 int ingenic_ecc_correct(struct ingenic_ecc *ecc, in ingenic_ecc_correct() argument
53 void ingenic_ecc_release(struct ingenic_ecc *ecc) in ingenic_ecc_release() argument
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| /linux-5.10/drivers/mtd/nand/ |
| D | ecc.c | 3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
28 * - prepare: Prepare an I/O request. Enable/disable the ECC engine based on
30 * engine, this step may involve to derive the ECC bytes and place
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| /linux-5.10/drivers/dma/ti/ |
| D | edma.c | 228 struct edma_cc *ecc; member
309 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
311 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
314 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
316 __raw_writel(val, ecc->base + offset); in edma_write()
319 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
322 unsigned val = edma_read(ecc, offset); in edma_modify()
326 edma_write(ecc, offset, val); in edma_modify()
329 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) in edma_and() argument
331 unsigned val = edma_read(ecc, offset); in edma_and()
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| /linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | nand-controller.yaml | 19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
49 nand-ecc-mode:
51 Desired ECC engine, either hardware (most of the time
54 and should be replaced by soft and nand-ecc-algo.
58 nand-ecc-engine:
62 A phandle on the hardware ECC engine if any. There are
64 1/ The ECC engine is part of the NAND controller, in this
66 2/ The ECC engine is part of the NAND part (on-die), in this
68 3/ The ECC engine is external, in this case the phandle should
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| D | gpmc-nand.txt | 10 For NAND specific properties such as ECC modes or bus width, please refer to
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
31 "ham1" 1-bit Hamming ecc code
32 "bch4" 4-bit BCH ecc code
33 "bch8" 8-bit BCH ecc code
34 "bch16" 16-bit BCH ECC code
35 Refer below "How to select correct ECC scheme for your device ?"
47 locating ECC errors for BCHx algorithms. SoC devices which have
49 Using ELM for ECC error correction frees some CPU cycles.
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| D | mtk-nand.txt | 5 the nand controller interface driver and the ECC engine driver.
23 - ecc-engine: Required ECC Engine node.
36 ecc-engine = <&bch>;
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
75 this number depends on max ecc step size
77 If max ecc step size supported is 1024,
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| D | hisi504-nand.txt | 11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
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| /linux-5.10/tools/perf/pmu-events/arch/s390/cf_z15/ |
| D | crypto6.json | 6 "BriefDescription": "ECC Function Count",
7 … "This counter counts the total number of the elliptic-curve cryptography (ECC) functions issued b…
13 "BriefDescription": "ECC Cycles Count",
14 … the total number of CPU cycles when the ECC coprocessor is busy performing the elliptic-curve cry…
20 "BriefDescription": "Ecc Blocked Function Count",
21 …ber of the elliptic-curve cryptography (ECC) functions that are issued by the CPU and are blocked …
27 "BriefDescription": "ECC Blocked Cycles Count",
28 …cycles blocked for the elliptic-curve cryptography (ECC) functions issued by the CPU because the E…
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| /linux-5.10/arch/arm/mach-socfpga/ |
| D | ocram.c | 23 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); in socfpga_init_ocram_ecc()
25 pr_err("Unable to find socfpga-ocram-ecc\n"); in socfpga_init_ocram_ecc()
32 pr_err("Unable to map OCRAM ecc regs.\n"); in socfpga_init_ocram_ecc()
36 /* Clear any pending OCRAM ECC interrupts, then enable ECC */ in socfpga_init_ocram_ecc()
60 /* ECC Manager Defines */
91 * This function uses the memory initialization block in the Arria10 ECC
92 * controller to initialize/clear the entire memory data and ECC data.
108 /* Clear any pending ECC interrupts */ in altr_init_memory_port()
127 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-ocram-ecc"); in socfpga_init_arria10_ocram_ecc()
129 pr_err("Unable to find socfpga-a10-ocram-ecc\n"); in socfpga_init_arria10_ocram_ecc()
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| /linux-5.10/Documentation/driver-api/ |
| D | mtdnand.rst | 357 Hardware ECC support
363 The nand driver supports three different types of hardware ECC.
367 Hardware ECC generator providing 3 bytes ECC per 256 byte.
371 Hardware ECC generator providing 3 bytes ECC per 512 byte.
375 Hardware ECC generator providing 6 bytes ECC per 512 byte.
379 Hardware ECC generator providing 8 bytes ECC per 512 byte.
396 Transfer the ECC from the hardware to the buffer. If the option
402 In case of an ECC error this function is called for error detection
409 Hardware ECC with syndrome calculation
412 Many hardware ECC implementations provide Reed-Solomon codes and
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