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/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
10 #include <linux/clk-provider.h>
30 #define PRG_ETH0_EXT_RMII_MODE 4
33 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
74 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
96 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, in meson8b_dwmac_mask_bits() argument
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Ddwmac-oxnas.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Oxford Semiconductor OXNAS DWMAC glue layer
35 #define DWMAC_LOW_TX_SOURCE 4
59 struct oxnas_dwmac *dwmac = priv; in oxnas_dwmac_init() local
64 ret = device_reset(dwmac->dev); in oxnas_dwmac_init()
68 ret = clk_prepare_enable(dwmac->clk); in oxnas_dwmac_init()
72 ret = regmap_read(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, &value); in oxnas_dwmac_init()
74 clk_disable_unprepare(dwmac->clk); in oxnas_dwmac_init()
91 regmap_write(dwmac->regmap, OXNAS_DWMAC_CTRL_REGOFFSET, value); in oxnas_dwmac_init()
94 value = DWMAC_TX_VARDELAY(4) | in oxnas_dwmac_init()
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Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
44 * ------------------------------------------------
47 * ------------------------------------------------
49 *| | clk-125/txclk | txclk |
50 * ------------------------------------------------
52 *| | clk-125/txclk | clkgen |
54 * ------------------------------------------------
56 *| | |clkgen/phyclk-in |
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Ddwmac-anarion.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adaptrum Anarion DWMAC glue layer
18 #define GMAC_SW_CONFIG_REG 4
29 return readl((void *)(gmac->ctl_block + reg)); in gmac_read_reg()
34 writel(val, (void *)(gmac->ctl_block + reg)); in gmac_write_reg()
47 sw_config |= (gmac->phy_intf_sel & GMAC_CONFIG_INTF_SEL_MASK); in anarion_gmac_init()
71 dev_err(&pdev->dev, "Cannot get reset region (%ld)!\n", in anarion_config_dt()
76 gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL); in anarion_config_dt()
78 return ERR_PTR(-ENOMEM); in anarion_config_dt()
80 gmac->ctl_block = (uintptr_t)ctl_block; in anarion_config_dt()
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Ddwmac-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * DWMAC Intel header file
18 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
19 #define SERDES_PWR_ST_SHIFT 4
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
26 /* General notes on dwmac-sun8i:
31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
59 /* struct sunxi_priv_data - hold all sunxi private data
67 * @mux_handle: Internal pointer used by mdio-mux lib
145 * co-packaged AC200 chip instead.
195 #define EMAC_RX_TH_MASK GENMASK(5, 4)
197 #define EMAC_RX_TH_64 (0x1 << 4)
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Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
23 #define PHY_INTF_RMII 4
24 #define RMII_CLK_SRC_RXC BIT(4)
30 #define ETH_DLY_GTXC_STAGES GENMASK(4, 0)
83 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
84 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
91 * configured, equals to (plat->variant->num_clks - 1) in default for all the case, in mt2712_set_interface()
94 plat->num_clks_to_config = plat->variant->num_clks - 1; in mt2712_set_interface()
97 switch (plat->phy_mode) { in mt2712_set_interface()
102 if (plat->rmii_clk_from_mac) in mt2712_set_interface()
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Ddwmac-ipq806x.c54 #define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4))
64 #define NSS_COMMON_CLK_DIV_SGMII_100 4
72 (0x13c + (4 * (x - 2))))
95 struct device *dev = &gmac->pdev->dev; in get_clk_div_sgmii()
113 return -EINVAL; in get_clk_div_sgmii()
121 struct device *dev = &gmac->pdev->dev; in get_clk_div_rgmii()
139 return -EINVAL; in get_clk_div_rgmii()
150 switch (gmac->phy_mode) { in ipq806x_gmac_set_speed()
153 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | in ipq806x_gmac_set_speed()
154 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); in ipq806x_gmac_set_speed()
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/linux-5.10/Documentation/devicetree/bindings/net/
Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
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Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.50a
25 - snps,dwmac-3.610
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Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel DWMAC glue layer Device Tree Bindings
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
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Dsocfpga-dwmac.txt1 Altera SOCFPGA SoC DWMAC controller
3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
12 Along with "snps,dwmac" and any applicable more detailed
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
25 DWMAC controller is connected emac splitter.
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Dqcom,ethqos.txt10 - compatible: Should be qcom,qcs404-ethqos"
12 - reg: Address and length of the register set for the device
14 - reg-names: Should contain register names "stmmaceth", "rgmii"
16 - clocks: Should contain phandle to clocks
18 - clock-names: Should contain clock names "stmmaceth", "pclk",
21 - interrupts: Should contain phandle to interrupts
23 - interrupt-names: Should contain interrupt names "macirq", "eth_lpi"
31 compatible = "qcom,qcs404-ethqos";
34 reg-names = "stmmaceth", "rgmii";
35 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
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/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
18 stdout-path = "serial0:115200n8";
22 compatible = "gpio-leds";
48 clock-frequency = <25000000>;
60 phy-mode = "rgmii";
61 phy-handle = <&phy0>;
63 max-frame-size = <9000>;
66 #address-cells = <1>;
67 #size-cells = <0>;
68 compatible = "snps,dwmac-mdio";
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/linux-5.10/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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Dox820.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/oxsemi,ox820.h>
10 #include <dt-bindings/reset/oxsemi,ox820.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 enable-method = "oxsemi,ox820-smp";
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Dlpc18xx.dtsi9 * Released under the terms of 3-clause BSD License
14 #include "armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
23 #address-cells = <1>;
24 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-m3";
40 compatible = "fixed-clock";
[all …]
Dstm32mp157c-odyssey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp157c-odyssey-som.dtsi"
11 model = "Seeed Studio Odyssey-STM32MP157C Board";
12 compatible = "seeed,stm32mp157c-odyssey",
13 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
21 stdout-path = "serial0:115200n8";
27 pinctrl-0 = <&ethernet0_rgmii_pins_a>;
28 pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
29 pinctrl-names = "default", "sleep";
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/linux-5.10/arch/arc/boot/dts/
Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
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Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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Dvdk_axs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&mb_intc>;
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 #clock-cells = <0>;
24 compatible = "fixed-clock";
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/linux-5.10/arch/mips/boot/dts/ni/
D169445.dts1 /dts-v1/;
4 #address-cells = <1>;
5 #size-cells = <1>;
9 #address-cells = <1>;
10 #size-cells = <0>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <50000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
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/linux-5.10/arch/arm64/boot/dts/qcom/
Dqcs404-evb-4000.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "qcs404-evb.dtsi"
11 compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
18 snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
19 snps,reset-active-low;
20 snps,reset-delays-us = <0 10000 10000>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&ethernet_defaults>;
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