/linux-5.10/Documentation/devicetree/bindings/pci/ |
D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface 3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 and thus inherits all the common properties defined in designware-pcie.txt. 7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; 8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; 9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; 10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; 11 - reg: base addresses and lengths of the PCIe controller (DBI), 13 - reg-names: Must include the following entries: 14 - "dbi" [all …]
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D | designware-pcie.txt | 1 * Synopsys DesignWare PCIe interface 4 - compatible: 5 "snps,dw-pcie" for RC mode; 6 "snps,dw-pcie-ep" for EP mode; 7 - reg: For designware cores version < 4.80 contains the configuration 10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for 15 - #address-cells: set to <3> 16 - #size-cells: set to <2> 17 - device_type: set to "pci" 18 - ranges: ranges for the PCI memory and I/O regions [all …]
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D | intel-gw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: PCIe RC controller on Intel Gateway SoCs 10 - Dilip Kota <eswara.kota@linux.intel.com> 16 const: intel,lgm-pcie 18 - compatible 23 - const: intel,lgm-pcie 24 - const: snps,dw-pcie [all …]
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D | spear13xx-pcie.txt | 1 SPEAr13XX PCIe DT detail: 4 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY 8 - compatible : should be "st,spear1340-pcie", "snps,dw-pcie". 9 - phys : phandle to PHY node associated with PCIe controller 10 - phy-names : must be "pcie-phy" 11 - All other definitions as per generic PCI bindings 14 - st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
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D | hisilicon-pcie.txt | 1 HiSilicon Hip05 and Hip06 PCIe host bridge DT description 3 HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. 4 It shares common functions with the PCIe DesignWare core driver and inherits 6 Documentation/devicetree/bindings/pci/designware-pcie.txt. 11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". 12 - reg: Should contain rc_dbi, config registers location and length. 13 - reg-names: Must include the following entries: 15 "config": PCIe configuration space registers. 16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts. 17 - port-id: Should be 0, 1, 2 or 3. [all …]
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D | samsung,exynos5440-pcie.txt | 1 * Samsung Exynos 5440 PCIe interface 3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 and thus inherits all the common properties defined in designware-pcie.txt. 7 - compatible: "samsung,exynos5440-pcie" 8 - reg: base addresses and lengths of the PCIe controller, 9 - reg-names : First name should be set to "elbi". 12 NOTE: When using the "config" property, reg-names must be set. 13 - interrupts: A list of interrupt outputs for level interrupt, 15 - phys: From PHY binding. Phandle for the generic PHY. 16 Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt [all …]
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D | pci-armada8k.txt | 1 * Marvell Armada 7K/8K PCIe interface 3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 and thus inherits all the common properties defined in designware-pcie.txt. 7 - compatible: "marvell,armada8k-pcie" 8 - reg: must contain two register regions 9 - the control register region 10 - the config space region 11 - reg-names: 12 - "ctrl" for the control register region 13 - "config" for the config space region [all …]
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D | amlogic,meson-pcie.txt | 1 Amlogic Meson AXG DWC PCIE SoC controller 3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. 4 It shares common functions with the PCIe DesignWare core driver and 6 Documentation/devicetree/bindings/pci/designware-pcie.txt. 11 - compatible: 13 - "amlogic,axg-pcie" for AXG SoC Family 14 - "amlogic,g12a-pcie" for G12A SoC Family 16 - reg: 18 - reg-names: Must be 19 - "elbi" External local bus interface registers [all …]
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D | qcom,pcie.txt | 3 - compatible: 7 - "qcom,pcie-ipq8064" for ipq8064 8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 9 - "qcom,pcie-apq8064" for apq8064 10 - "qcom,pcie-apq8084" for apq8084 11 - "qcom,pcie-msm8996" for msm8996 or apq8096 12 - "qcom,pcie-ipq4019" for ipq4019 13 - "qcom,pcie-ipq8074" for ipq8074 14 - "qcom,pcie-qcs404" for qcs404 15 - "qcom,pcie-sdm845" for sdm845 [all …]
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D | uniphier-pcie.txt | 1 Socionext UniPhier PCIe host controller bindings 3 This describes the devicetree bindings for PCIe host controller implemented 6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. 7 It shares common functions with the PCIe DesignWare core driver and inherits 9 Documentation/devicetree/bindings/pci/designware-pcie.txt. 12 - compatible: Should be "socionext,uniphier-pcie". 13 - reg: Specifies offset and length of the register set for the device. 14 According to the reg-names, appropriate register sets are required. 15 - reg-names: Must include the following entries: 16 "dbi" - controller configuration registers [all …]
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D | fsl,imx6q-pcie.txt | 1 * Freescale i.MX6 PCIe interface 3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP 4 and thus inherits all the common properties defined in designware-pcie.txt. 7 - compatible: 8 - "fsl,imx6q-pcie" 9 - "fsl,imx6sx-pcie", 10 - "fsl,imx6qp-pcie" 11 - "fsl,imx7d-pcie" 12 - "fsl,imx8mq-pcie" 13 - reg: base address and length of the PCIe controller [all …]
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D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Will Deacon <will@kernel.org> 13 Firmware-initialised PCI host controllers and PCI emulations, such as the 14 virtio-pci implementations found in kvmtool and other para-virtualised 21 Configuration Space is assumed to be memory-mapped (as opposed to being 26 For CAM, this 24-bit offset is: 41 - description: [all …]
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/linux-5.10/drivers/dma/dw-edma/ |
D | dw-edma-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare eDMA PCIe driver 14 #include <linux/pci-epf.h> 17 #include "dw-edma-core.h" 69 const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; in dw_edma_pcie_probe() 70 struct device *dev = &pdev->dev; in dw_edma_pcie_probe() 73 struct dw_edma *dw; in dw_edma_pcie_probe() local 83 err = pcim_iomap_regions(pdev, BIT(pdata->rg_bar) | in dw_edma_pcie_probe() 84 BIT(pdata->ll_bar) | in dw_edma_pcie_probe() [all …]
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D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0 3 obj-$(CONFIG_DW_EDMA) += dw-edma.o 4 dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o 5 dw-edma-objs := dw-edma-core.o \ 6 dw-edma-v0-core.o $(dw-edma-y) 7 obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
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/linux-5.10/drivers/pci/controller/ |
D | pcie-altera.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved 6 * Description: Altera PCIe host controller driver 45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument 46 (((pcie)->hip_base) + (reg) + (1 << 20)) 47 #define S10_RP_SECONDARY(pcie) \ argument 48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) 60 #define TLP_CFG_DW0(pcie, cfg) \ argument 63 #define TLP_CFG_DW1(pcie, tag, be) \ argument 64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be)) [all …]
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D | pci-host-generic.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Simple, generic PCI host controller driver targeting firmware-initialised 14 #include <linux/pci-ecam.h> 28 struct pci_config_window *cfg = bus->sysdata; in pci_dw_valid_device() 31 * The Synopsys DesignWare PCIe controller in ECAM mode will not filter in pci_dw_valid_device() 36 if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) in pci_dw_valid_device() 61 { .compatible = "pci-host-cam-generic", 64 { .compatible = "pci-host-ecam-generic", 67 { .compatible = "marvell,armada8k-pcie-ecam", 70 { .compatible = "socionext,synquacer-pcie-ecam", [all …]
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/linux-5.10/drivers/pci/controller/dwc/ |
D | pcie-designware-plat.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe RC driver for Synopsys DesignWare Core 5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 22 #include "pcie-designware.h" 49 pp->num_vectors = MAX_MSI_IRQS; in dw_plat_set_num_vectors() 89 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in dw_plat_pcie_ep_raise_irq() 116 struct dw_pcie *pci = dw_plat_pcie->pci; in dw_plat_add_pcie_port() 117 struct pcie_port *pp = &pci->pp; in dw_plat_add_pcie_port() 118 struct device *dev = &pdev->dev; in dw_plat_add_pcie_port() 121 pp->irq = platform_get_irq(pdev, 1); in dw_plat_add_pcie_port() [all …]
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D | pcie-al.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips 12 #include <linux/pci-ecam.h> 13 #include <linux/pci-acpi.h> 25 struct pci_config_window *cfg = bus->sysdata; in al_pcie_map_bus() 26 struct al_pcie_acpi *pcie = cfg->priv; in al_pcie_map_bus() local 27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus() 29 if (bus->number == cfg->busr.start) { in al_pcie_map_bus() 31 * The DW PCIe core doesn't filter out transactions to other in al_pcie_map_bus() 45 struct device *dev = cfg->parent; in al_pcie_init() [all …]
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/linux-5.10/arch/arm64/boot/dts/marvell/ |
D | armada-cp11x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/interrupt-controller/mvebu-icu.h> 9 #include <dt-bindings/thermal/thermal.h> 11 #include "armada-common.dtsi" 27 thermal-zones { 28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { 29 polling-delay-passive = <0>; /* Interrupt driven */ 30 polling-delay = <0>; /* Interrupt driven */ 32 thermal-sensors = <&CP11X_LABEL(thermal) 0>; 42 cooling-maps { }; [all …]
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/linux-5.10/arch/arm/boot/dts/ |
D | spear1310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 15 compatible = "st,spear-spics-gpio"; 17 st-spics,peripcfg-reg = <0x3b0>; 18 st-spics,sw-enable-bit = <12>; 19 st-spics,cs-value-bit = <11>; 20 st-spics,cs-enable-mask = <3>; 21 st-spics,cs-enable-shift = <8>; 22 gpio-controller; 23 #gpio-cells = <2>; 27 compatible = "st,spear1310-miphy"; [all …]
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D | armada-39x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 31 #address-cells = <1>; 32 #size-cells = <0>; 33 enable-method = "marvell,armada-390-smp"; 37 compatible = "arm,cortex-a9"; [all …]
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D | bcm-cygnus.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h> 34 #include <dt-bindings/interrupt-controller/irq.h> 35 #include <dt-bindings/clock/bcm-cygnus.h> 38 #address-cells = <1>; 39 #size-cells = <1>; 42 interrupt-parent = <&gic>; 54 #address-cells = <1>; 55 #size-cells = <0>; 59 compatible = "arm,cortex-a9"; 60 next-level-cache = <&L2>; [all …]
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D | imx6qp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 10 compatible = "mmio-sram"; 16 compatible = "mmio-sram"; 23 compatible = "fsl,imx6qp-pre"; 27 clock-names = "axi"; 32 compatible = "fsl,imx6qp-pre"; 36 clock-names = "axi"; 41 compatible = "fsl,imx6qp-pre"; 45 clock-names = "axi"; 50 compatible = "fsl,imx6qp-pre"; [all …]
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D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC 4 * This file is dual-licensed: you can use it either under the terms 43 #include <dt-bindings/interrupt-controller/arm-gic.h> 44 #include <dt-bindings/dma/nbpfaxi.h> 45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h> 48 #address-cells = <1>; 49 #size-cells = <1>; 51 interrupt-parent = <&intc>; 54 #address-cells = <1>; 55 #size-cells = <0>; [all …]
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/linux-5.10/arch/arm64/boot/dts/broadcom/northstar2/ |
D | ns2.dtsi | 35 #include <dt-bindings/interrupt-controller/arm-gic.h> 36 #include <dt-bindings/clock/bcm-ns2.h> 40 interrupt-parent = <&gic>; 41 #address-cells = <2>; 42 #size-cells = <2>; 45 #address-cells = <2>; 46 #size-cells = <0>; 50 compatible = "arm,cortex-a57"; 52 enable-method = "psci"; 53 next-level-cache = <&CLUSTER0_L2>; [all …]
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