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Searched +full:duty +full:- +full:cycle (Results 1 – 25 of 256) sorted by relevance

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/linux/drivers/pwm/
H A Dpwm-ntxec.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * e-book readers designed by the original design manufacturer Netronix, Inc.
13 * - The get_state callback is not implemented, because the current state of
15 * - The hardware can only generate normal polarity output.
16 * - The period and duty cycl
57 ntxec_pwm_set_raw_period_and_duty_cycle(struct pwm_chip * chip,int period,int duty) ntxec_pwm_set_raw_period_and_duty_cycle() argument
86 unsigned int period, duty; ntxec_pwm_apply() local
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H A Dpwm-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
7 * with the old duty cycle and the new period. This is because the counters
9 * automatically reloaded at the end of a cycle
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H A Dpwm-iqs620a.c1 // SPDX-License-Identifier: GPL-2.0+
8 * - The period is fixed to 1 ms and is generated continuously despite changes
9 * to the duty cycle or enable/disable state.
10 * - Changes to the duty cycle or enable/disable state take effect immediately
12 * - Th
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H A Dpwm-microchip-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
17 * As setting the period/duty cycle take
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H A Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
20 * - When PWM is stopped, timer counter gets stopped immediately. This
22 * - When PWM is running and changing both duty cycle an
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H A Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
12 * hard-tied to 0 (XNOR), which effectively inverts the comparison so that
19 * To compensate, this driver always **inverts** the duty value when reading
21 * **active-high** PWM interface.
25 * - Whe
130 u32 duty, val, inactive; pwm_sifive_get_state() local
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H A Dpwm-sprd.c1 // SPDX-License-Identifier: GPL-2.0
60 return readl_relaxed(spc->base + offset); in sprd_pwm_read()
68 writel_relaxed(val, spc->base + offset); in sprd_pwm_write()
75 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
76 u32 val, duty, prescale; in sprd_pwm_get_state() local
84 ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks); in sprd_pwm_get_state()
87 pwm->hwpw in sprd_pwm_get_state()
127 u32 prescale, duty; sprd_pwm_config() local
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H A Dpwm-loongson.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2025 Loongson Technology Corporation Limited.
8 * Reference Manual: https://loongson.github.io/LoongArch-Documentation/Loongson-7A1000-usermanual-EN.pdf
15 * - I
121 u64 duty, period; pwm_loongson_config() local
169 u32 duty, period, ctrl; pwm_loongson_get_state() local
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/linux/Documentation/devicetree/bindings/regulator/
H A Dpwm-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Le
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/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 --------
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H A Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 ---------
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H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 ----
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H A Dmax31790.rst10 Addresses scanned: -
18 ---------
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H A Df71882fg.rst103 This is the 64-pin variant of the F71889FG, they have the
119 ---------
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H A Dw83792d.rst10 Addresses scanned: I2C 0x2c - 0x2f
19 ---------
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/linux/Documentation/devicetree/bindings/input/
H A Dpwm-vibrator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/pwm-vibrato
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/linux/Documentation/driver-api/thermal/
H A Dcpu-idle-cooling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 -------
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/linux/Documentation/userspace-api/media/rc/
H A Dlirc-set-send-duty-cycle.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
13 LIRC_SET_SEND_DUTY_CYCLE - Set the duty cycl
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 dce_panel_cntl->base.ctx
40 dce_panel_cntl->base.ctx->logger
43 dce_panel_cntl->regs->reg
47 dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_nam
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/linux/sound/pcmcia/pdaudiocf/
H A Dpdaudiocf.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
31 #define PDAUDIOCF_TESTDATASEL (1<<1) /* test data selection, 0 = 0x55, 1 = pseudo-random */
43 #define PDAUDIOCF_DATAFMT0 (1<<10) /* data format bits: 00 = 16-bit, 01 = 18-bit */
44 #define PDAUDIOCF_DATAFMT1 (1<<11) /* 10 = 20-bit, 11 = 24-bi
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/linux/drivers/clk/meson/
H A Dsclk-div.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 * The duty cycle may also be set for the LR clock variant. The duty cycle
15 * hi = [0 - val]
19 #include <linux/clk-provider.h>
22 #include "clk-regma
126 sclk_div_set_duty_cycle(struct clk_hw * hw,struct clk_duty * duty) sclk_div_set_duty_cycle() argument
140 sclk_div_get_duty_cycle(struct clk_hw * hw,struct clk_duty * duty) sclk_div_get_duty_cycle() argument
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/linux/drivers/clk/
H A Dclk-scmi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2024 ARM Ltd.
9 #include <linux/clk-provider.h>
51 ret = scmi_proto_clk_ops->rate_get(clk->ph, clk->id, &rate); in scmi_clk_recalc_rate()
69 if (clk->info->rate_discret in scmi_clk_round_rate()
183 scmi_clk_get_duty_cycle(struct clk_hw * hw,struct clk_duty * duty) scmi_clk_get_duty_cycle() argument
203 scmi_clk_set_duty_cycle(struct clk_hw * hw,struct clk_duty * duty) scmi_clk_set_duty_cycle() argument
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/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-pinephone-1.1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-a64-pinephone.dtsi"
10 compatible = "pine64,pinephone-1.1", "pine64,pinephone", "allwinner,sun50i-a64";
14 power-supply = <&reg_ldo_io0>;
17 * 1.0, and the lowest PWM duty cycl
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dadt7475.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jea
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/linux/drivers/leds/
H A Dleds-ipaq-micro.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/mfd/ipaq-micro.h>
24 struct ipaq_micro *micro = dev_get_drvdata(led_cdev->dev->parent->parent); in micro_leds_brightness_set()
45 msg.tx_data[2] = 0; /* Duty cycle 25 in micro_leds_brightness_set()
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