Searched +full:dual +full:- +full:lane (Results 1 – 2 of 2) sorted by relevance
| /qemu/target/hexagon/imported/mmvec/ |
| H A D | ext.idef | 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
148 * MMVECTOR MEMORY OPERATIONS - NO NAPALI V1
308 * MMVECTOR MEMORY OPERATIONS - NON TEMPORAL
314 MMVEC_EACH_EA(vS32b_nt,"Aligned Vector Store - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_STORE,A_RESTRIC…
315 MMVEC_COND_EACH_EA(vS32b_nt,"Aligned Vector Store - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_STORE,A_RE…
317 MMVEC_EACH_EA(vS32b_nt_new,"Aligned Vector Store New - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_STORE,A…
318 MMVEC_COND_EACH_EA(vS32b_nt_new,"Aligned Vector Store New - Non temporal",ATTRIBS(ATTR_VMEM_NT,A_ST…
321 MMVEC_STQ(vS32b_nt, "Aligned Vector Store - Non temporal", ATTRIBS(ATTR_VMEM_NT,A_STORE,A_RES…
323 MMVEC_LD(vL32b_nt, "Aligned Vector Load - Non temporal", ATTRIBS(ATTR_VMEM_NT,A_LOAD,A_CVI_V…
324 MMVEC_LDC(vL32b_nt, "Aligned Vector Load Cur - Non temporal", ATTRIBS(ATTR_VMEM_NT,A_LOAD,A_CVI_NE…
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| /qemu/target/arm/tcg/ |
| H A D | mve_helper.c | 2 * M-profile MVE Operations
24 #include "exec/helper-proto.h"
25 #include "accel/tcg/cpu-ldst.h"
39 if ((env->condexec_bits & 0xf) != 0) { in mve_eci_mask()
43 eci = env->condexec_bits >> 4; in mve_eci_mask()
64 * (1) by default, we update every lane in the vector in mve_element_mask()
66 * (3) low-overhead-branch tail predication will mask out part in mve_element_mask()
70 * We combine all these into a 16-bit result with the same semantics in mve_element_mask()
71 * as VPR.P0: 0 to mask the lane, 1 if it is active. in mve_element_mask()
72 * 8-bit vector ops will look at all bits of the result; in mve_element_mask()
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