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/linux-6.15/drivers/gpu/drm/panel/
Dpanel-novatek-nt36523.c26 #define mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, cmd, seq...) \ argument
28 mipi_dsi_dcs_write_seq(dsi0, cmd, seq); \
68 struct mipi_dsi_device *dsi0 = pinfo->dsi[0]; in elish_boe_init_sequence() local
71 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10); in elish_boe_init_sequence()
72 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
73 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xb9, 0x05); in elish_boe_init_sequence()
74 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x20); in elish_boe_init_sequence()
75 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xfb, 0x01); in elish_boe_init_sequence()
76 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40); in elish_boe_init_sequence()
77 mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xff, 0x10); in elish_boe_init_sequence()
[all …]
/linux-6.15/drivers/gpu/drm/vc4/tests/
Dvc4_test_pv_muxing.c199 VC4_PV_MUXING_TEST("1 output: DSI0",
211 VC4_PV_MUXING_TEST("2 outputs: DSI0, HDMI0",
214 VC4_PV_MUXING_TEST("2 outputs: DSI0, VEC",
217 VC4_PV_MUXING_TEST("2 outputs: DSI0, DSI1",
220 VC4_PV_MUXING_TEST("2 outputs: DSI0, TXP",
247 VC4_PV_MUXING_TEST("3 outputs: DSI0, HDMI0, DSI1",
251 VC4_PV_MUXING_TEST("3 outputs: DSI0, HDMI0, TXP",
255 VC4_PV_MUXING_TEST("3 outputs: DSI0, VEC, DSI1",
259 VC4_PV_MUXING_TEST("3 outputs: DSI0, VEC, TXP",
286 VC4_PV_MUXING_TEST("DPI/DSI0 Conflict",
[all …]
/linux-6.15/Documentation/devicetree/bindings/clock/
Dbrcm,bcm2835-cprman.txt25 - DSI0 byte clock
26 - DSI0 DDR2 clock
27 - DSI0 DDR clock
Dqcom,sa8775p-dispcc.yaml34 - description: Byte clock from DSI0 PHY
35 - description: Pixel clock from DSI0 PHY
/linux-6.15/drivers/soc/mediatek/
Dmt8167-mmsys.h26 MMSYS_ROUTE(RDMA0, DSI0,
29 MMSYS_ROUTE(RDMA0, DSI0,
Dmt8365-mmsys.h43 MMSYS_ROUTE(DITHER0, DSI0,
46 MMSYS_ROUTE(DITHER0, DSI0,
Dmt8192-mmsys.h40 MMSYS_ROUTE(DITHER0, DSI0,
49 MMSYS_ROUTE(DITHER0, DSI0,
Dmt8173-mmsys.h42 MMSYS_ROUTE(UFOE, DSI0,
60 MMSYS_ROUTE(UFOE, DSI0,
Dmt8186-mmsys.h78 MMSYS_ROUTE(DITHER0, DSI0,
81 MMSYS_ROUTE(DITHER0, DSI0,
Dmt8195-mmsys.h238 MMSYS_ROUTE(DSC0, DSI0,
241 MMSYS_ROUTE(DITHER0, DSI0,
292 MMSYS_ROUTE(DITHER0, DSI0,
346 MMSYS_ROUTE(DSC0, DSI0,
Dmt8188-mmsys.h214 MMSYS_ROUTE(DITHER0, DSI0,
232 MMSYS_ROUTE(DSC0, DSI0,
241 MMSYS_ROUTE(DITHER0, DSI0,
262 MMSYS_ROUTE(DSC0, DSI0,
Dmt8183-mmsys.h40 MMSYS_ROUTE(DITHER0, DSI0,
/linux-6.15/Documentation/devicetree/bindings/display/
Dbrcm,bcm2835-dsi0.yaml4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#
22 - brcm,bcm2835-dsi0
/linux-6.15/arch/arm/boot/dts/broadcom/
Dbcm283x.dtsi96 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
358 dsi0: dsi@7e209000 { label
359 compatible = "brcm,bcm2835-dsi0";
Dbcm2835-rpi.dtsi78 &dsi0 {
/linux-6.15/drivers/pinctrl/sunxi/
Dpinctrl-sun50i-a100.c204 SUNXI_FUNCTION(0x4, "dsi0"), /* DP0 */
211 SUNXI_FUNCTION(0x4, "dsi0"), /* DM0 */
218 SUNXI_FUNCTION(0x4, "dsi0"), /* DP1 */
225 SUNXI_FUNCTION(0x4, "dsi0"), /* DM1 */
232 SUNXI_FUNCTION(0x4, "dsi0"), /* CKP */
239 SUNXI_FUNCTION(0x4, "dsi0"), /* CKM */
246 SUNXI_FUNCTION(0x4, "dsi0"), /* DP2 */
253 SUNXI_FUNCTION(0x4, "dsi0"), /* DM2 */
260 SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
267 SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
/linux-6.15/Documentation/devicetree/bindings/display/panel/
Dstartek,kd070fhfid015.yaml49 dsi0 {
Dnovatek,nt36672a.yaml68 dsi0 {
/linux-6.15/drivers/gpu/drm/renesas/rz-du/
Drzg2l_du_drv.h34 * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data
/linux-6.15/arch/arm64/boot/dts/rockchip/
Drk3566-powkiddy-rgb30.dts22 &dsi0 {
Drk3566-powkiddy-rk2023.dts22 &dsi0 {
Drk3566-powkiddy-rgb10max3.dts26 &dsi0 {
Drk3566-powkiddy-rgb20sx.dts52 &dsi0 {
/linux-6.15/arch/arm64/boot/dts/mediatek/
Dmt8395-radxa-nio-12l-8-hd-panel.dtso23 &dsi0 {
/linux-6.15/drivers/gpu/drm/vc4/
Dvc4_dsi.c7 * DOC: VC4 DSI0/DSI1 module
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
14 * while the compute module brings both DSI0 and DSI1 out.
17 * currently, with most of the information necessary for DSI0
539 /* Whether we're on bcm2835's DSI0 or DSI1. */
624 /* DSI0 should be able to write normally. */ in dsi_dma_workaround_write()
1461 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },

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