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/linux-6.8/Documentation/devicetree/bindings/arm/
Dqcom,coresight-tpdm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Trace, Profiling and Diagnostics Monitor - TPDM
13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
14 Single Bit (DSB). It performs data collection in the data producing clock
22 - Mao Jinlong <quic_jinlmao@quicinc.com>
23 - Tao Zhang <quic_taozha@quicinc.com>
31 - qcom,coresight-tpdm
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/linux-6.8/drivers/hwtracing/coresight/
Dcoresight-tpda.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "coresight-priv.h"
19 #include "coresight-tpda.h"
20 #include "coresight-trace-id.h"
26 return (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && in coresight_device_is_tpdm()
27 (csdev->subtype.source_subtype == in coresight_device_is_tpdm()
32 * Read the DSB element size from the TPDM device
34 * The dsb element size read from the devicetree if available.
35 * 0 - Otherwise, with a warning once.
40 u8 size = 0; in tpdm_read_dsb_element_size() local
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Dcoresight-tpda.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* Aggregator port DSB data set element size bit */
22 * struct tpda_drvdata - specifics associated to an TPDA component
Dcoresight-etm4x-core.c1 // SPDX-License-Identifier: GPL-2.0
25 #include <linux/coresight-pmu.h>
34 #include <linux/clk/clk-conf.h>
42 #include "coresight-etm4x.h"
43 #include "coresight-etm-perf.h"
44 #include "coresight-etm4x-cfg.h"
45 #include "coresight-self-hosted-trace.h"
46 #include "coresight-syscfg.h"
47 #include "coresight-trace-id.h"
53 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
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/linux-6.8/drivers/irqchip/
Dirq-gic-v3-its.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
40 #include "irq-gic-common.h"
65 * Collection structure - just an ID, and a redistributor address to
75 * The ITS_BASER structure - contains memory information, cached
76 * value of BASER register configuration and ITS page size.
88 * The ITS structure - contains most of the infrastructure, with the
89 * top-level MSI domain, the command queue, the collections, and the
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/linux-6.8/arch/arm/probes/kprobes/
Dtest-thumb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/probes/kprobes/test-thumb.c
13 #include "test-core.h"
89 TEST_GROUP("16-bit Thumb data-processing instructions") in kprobe_thumb16_test_cases()
118 TEST_R( "add sp" ", r",8,-8, "") in kprobe_thumb16_test_cases()
120 TEST_BF_R("add pc" ", r",0,2f-1f-8,"") in kprobe_thumb16_test_cases()
125 TEST_R( "cmp sp" ", r",8,-8, "") in kprobe_thumb16_test_cases()
130 TEST_P( "mov sp, r",8,-8, "") in kprobe_thumb16_test_cases()
164 TEST_GROUP("16-bit Thumb Load/store instructions") in kprobe_thumb16_test_cases()
204 TEST_GROUP("Generate PC-/SP-relative address") in kprobe_thumb16_test_cases()
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/linux-6.8/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
12 * by size in bits. For example [RW 32]. The access types are:
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
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Dbnx2x_main.c3 * Copyright (c) 2007-2013 Broadcom Corporation
36 #include <linux/dma-mapping.h>
83 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
84 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
85 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
86 #define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw"
87 #define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw"
88 #define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw"
117 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
124 static int mrrs = -1;
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