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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.c33 static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) in irq_reset() argument
35 intel_de_write(display, regs.imr, 0xffffffff); in irq_reset()
36 intel_de_posting_read(display, regs.imr); in irq_reset()
38 intel_de_write(display, regs.ier, 0); in irq_reset()
41 intel_de_write(display, regs.iir, 0xffffffff); in irq_reset()
42 intel_de_posting_read(display, regs.iir); in irq_reset()
43 intel_de_write(display, regs.iir, 0xffffffff); in irq_reset()
44 intel_de_posting_read(display, regs.iir); in irq_reset()
50 static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg) in assert_iir_is_zero() argument
52 u32 val = intel_de_read(display, reg); in assert_iir_is_zero()
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H A Dintel_pch.c43 * Check for platforms where the south display is on the same PCI device or SoC
44 * die as the north display. The PCH (if it even exists) is not involved in
45 * display. Return a fake PCH type for south display handling on these
48 static enum intel_pch intel_pch_fake_for_south_display(struct intel_display *display) in intel_pch_fake_for_south_display() argument
52 if (DISPLAY_VER(display) >= 20) in intel_pch_fake_for_south_display()
54 else if (display->platform.battlemage || display->platform.meteorlake) in intel_pch_fake_for_south_display()
56 else if (display->platform.dg2) in intel_pch_fake_for_south_display()
58 else if (display->platform.dg1) in intel_pch_fake_for_south_display()
66 intel_pch_type(const struct intel_display *display, unsigned short id) in intel_pch_type() argument
70 drm_dbg_kms(display->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
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H A Dintel_display_power_well.c45 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) in pw_idx_to_pg() argument
47 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; in pw_idx_to_pg()
67 void (*sync_hw)(struct intel_display *display,
74 void (*enable)(struct intel_display *display,
80 void (*disable)(struct intel_display *display,
83 bool (*is_enabled)(struct intel_display *display,
94 lookup_power_well(struct intel_display *display, in lookup_power_well() argument
99 for_each_power_well(display, power_well) in lookup_power_well()
106 * to abort things like display initialization sequences. Just return in lookup_power_well()
110 drm_WARN(display->drm, 1, in lookup_power_well()
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H A Di9xx_display_sr.c15 static void i9xx_display_save_swf(struct intel_display *display) in i9xx_display_save_swf() argument
20 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_save_swf()
22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
27 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
30 } else if (HAS_GMCH(display)) { in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
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H A Dintel_fdi.c29 static void assert_fdi_tx(struct intel_display *display, in assert_fdi_tx() argument
34 if (HAS_DDI(display)) { in assert_fdi_tx()
42 cur_state = intel_de_read(display, in assert_fdi_tx()
43 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; in assert_fdi_tx()
45 cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
47 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, in assert_fdi_tx()
52 void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe) in assert_fdi_tx_enabled() argument
54 assert_fdi_tx(display, pipe, true); in assert_fdi_tx_enabled()
57 void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe) in assert_fdi_tx_disabled() argument
59 assert_fdi_tx(display, pipe, false); in assert_fdi_tx_disabled()
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H A Dintel_pch_display.c25 bool intel_has_pch_trancoder(struct intel_display *display, in intel_has_pch_trancoder() argument
28 return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) || in intel_has_pch_trancoder()
29 (HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
34 struct intel_display *display = to_intel_display(crtc); in intel_crtc_pch_transcoder() local
36 if (HAS_PCH_LPT(display)) in intel_crtc_pch_transcoder()
42 static void assert_pch_dp_disabled(struct intel_display *display, in assert_pch_dp_disabled() argument
49 state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe); in assert_pch_dp_disabled()
51 INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, in assert_pch_dp_disabled()
55 INTEL_DISPLAY_STATE_WARN(display, in assert_pch_dp_disabled()
56 HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
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H A Dintel_pch_refclk.c18 static void lpt_fdi_reset_mphy(struct intel_display *display) in lpt_fdi_reset_mphy() argument
22 intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL); in lpt_fdi_reset_mphy()
24 ret = intel_de_wait_for_set_us(display, SOUTH_CHICKEN2, in lpt_fdi_reset_mphy()
27 drm_err(display->drm, "FDI mPHY reset assert timeout\n"); in lpt_fdi_reset_mphy()
29 intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0); in lpt_fdi_reset_mphy()
31 ret = intel_de_wait_for_clear_us(display, SOUTH_CHICKEN2, in lpt_fdi_reset_mphy()
34 drm_err(display->drm, "FDI mPHY reset de-assert timeout\n"); in lpt_fdi_reset_mphy()
38 static void lpt_fdi_program_mphy(struct intel_display *display) in lpt_fdi_program_mphy() argument
42 lpt_fdi_reset_mphy(display); in lpt_fdi_program_mphy()
44 tmp = intel_sbi_read(display, 0x8008, SBI_MPHY); in lpt_fdi_program_mphy()
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H A Dintel_gmbus.c36 #include <drm/display/drm_hdcp_helper.h>
54 struct intel_display *display; member
155 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, in get_gmbus_pin() argument
161 if (INTEL_PCH_TYPE(display) >= PCH_MTL) { in get_gmbus_pin()
164 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { in get_gmbus_pin()
167 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { in get_gmbus_pin()
170 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { in get_gmbus_pin()
173 } else if (HAS_PCH_CNP(display)) { in get_gmbus_pin()
176 } else if (display->platform.geminilake || display->platform.broxton) { in get_gmbus_pin()
179 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin()
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H A Dintel_dmc.c48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
49 * engine to save and restore the state of display engine when it enter into
65 struct intel_display *display; member
87 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
89 return display->dmc.dmc; in display_to_dmc()
92 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
94 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
99 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
101 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
188 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
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H A Dintel_cdclk.c60 * The display engine uses several different clocks to do its work. There
63 * are the core display clock (CDCLK) and RAWCLK.
65 * CDCLK clocks most of the display pipe logic, and thus its frequency
71 * to minimize power consumption for a given display configuration.
72 * Typically changes to the CDCLK frequency require all the display pipes
161 void (*get_cdclk)(struct intel_display *display,
163 void (*set_cdclk)(struct intel_display *display,
170 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
173 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
176 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
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H A Dintel_fbc.c28 * compressing the amount of memory used by the display. It is total
33 * and having fewer memory pages opened and accessed for refreshing the display.
96 struct intel_display *display; member
130 static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe) in intel_fbc_for_pipe() argument
132 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_fbc_for_pipe()
137 if (drm_WARN_ON(display->drm, !primary)) in intel_fbc_for_pipe()
173 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
187 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
201 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
210 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
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H A Dintel_de.h15 static inline struct intel_uncore *__to_uncore(struct intel_display *display) in __to_uncore() argument
17 return to_intel_uncore(display->drm); in __to_uncore()
21 intel_de_read(struct intel_display *display, i915_reg_t reg) in intel_de_read() argument
25 intel_dmc_wl_get(display, reg); in intel_de_read()
27 val = intel_uncore_read(__to_uncore(display), reg); in intel_de_read()
29 intel_dmc_wl_put(display, reg); in intel_de_read()
35 intel_de_read8(struct intel_display *display, i915_reg_t reg) in intel_de_read8() argument
39 intel_dmc_wl_get(display, reg); in intel_de_read8()
41 val = intel_uncore_read8(__to_uncore(display), reg); in intel_de_read8()
43 intel_dmc_wl_put(display, reg); in intel_de_read8()
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H A Dvlv_dsi.c91 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local
97 if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
99 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
102 static void write_data(struct intel_display *display, in write_data() argument
114 intel_de_write(display, reg, val); in write_data()
118 static void read_data(struct intel_display *display, in read_data() argument
125 u32 val = intel_de_read(display, reg); in read_data()
137 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer() local
152 data_reg = MIPI_LP_GEN_DATA(display, port); in intel_dsi_host_transfer()
154 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); in intel_dsi_host_transfer()
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H A Dintel_combo_phy.c58 icl_get_procmon_ref_values(struct intel_display *display, enum phy phy) in icl_get_procmon_ref_values() argument
62 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
80 static void icl_set_procmon_ref_values(struct intel_display *display, in icl_set_procmon_ref_values() argument
85 procmon = icl_get_procmon_ref_values(display, phy); in icl_set_procmon_ref_values()
87 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
90 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
91 intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
94 static bool check_phy_reg(struct intel_display *display, in check_phy_reg() argument
98 u32 val = intel_de_read(display, reg); in check_phy_reg()
101 drm_dbg_kms(display->drm, in check_phy_reg()
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H A Dintel_flipq.c98 struct intel_display *display = to_intel_display(crtc); in intel_flipq_crtc_init() local
107 drm_dbg_kms(display->drm, "[CRTC:%d:%s] FQ %d: start 0x%x\n", in intel_flipq_crtc_init()
113 bool intel_flipq_supported(struct intel_display *display) in intel_flipq_supported() argument
115 if (!display->params.enable_flipq) in intel_flipq_supported()
118 if (!display->dmc.dmc) in intel_flipq_supported()
121 if (DISPLAY_VER(display) == 20) in intel_flipq_supported()
125 return DISPLAY_VER(display) >= 30 && intel_vrr_always_use_vrr_tg(display); in intel_flipq_supported()
128 void intel_flipq_init(struct intel_display *display) in intel_flipq_init() argument
132 intel_dmc_wait_fw_load(display); in intel_flipq_init()
134 for_each_intel_crtc(display->drm, crtc) in intel_flipq_init()
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H A Dintel_wm.c18 * @display: display device
49 void intel_update_watermarks(struct intel_display *display) in intel_update_watermarks() argument
51 if (display->funcs.wm->update_wm) in intel_update_watermarks()
52 display->funcs.wm->update_wm(display); in intel_update_watermarks()
58 struct intel_display *display = to_intel_display(state); in intel_wm_compute() local
60 if (!display->funcs.wm->compute_watermarks) in intel_wm_compute()
63 return display->funcs.wm->compute_watermarks(state, crtc); in intel_wm_compute()
69 struct intel_display *display = to_intel_display(state); in intel_initial_watermarks() local
71 if (display->funcs.wm->initial_watermarks) { in intel_initial_watermarks()
72 display->funcs.wm->initial_watermarks(state, crtc); in intel_initial_watermarks()
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H A Dintel_vrr.c35 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
39 if (!HAS_VRR(display)) in intel_vrr_is_capable()
98 static int intel_vrr_extra_vblank_delay(struct intel_display *display) in intel_vrr_extra_vblank_delay() argument
106 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_extra_vblank_delay()
109 static int intel_vrr_vmin_flipline_offset(struct intel_display *display) in intel_vrr_vmin_flipline_offset() argument
119 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_vmin_flipline_offset()
177 struct intel_display *display = to_intel_display(crtc_state); in is_cmrr_frac_required() local
182 if (!HAS_CMRR(display) || true) in is_cmrr_frac_required()
263 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_hw_value() local
269 if (DISPLAY_VER(display) >= 13) in intel_vrr_hw_value()
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H A Dintel_bw.c73 static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, in dg1_mchbar_read_qgv_point_info() argument
77 struct intel_uncore *uncore = to_intel_uncore(display->drm); in dg1_mchbar_read_qgv_point_info()
109 static int icl_pcode_read_qgv_point_info(struct intel_display *display, in icl_pcode_read_qgv_point_info() argument
117 ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in icl_pcode_read_qgv_point_info()
124 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
137 static int adls_pcode_read_psf_gv_point_info(struct intel_display *display, in adls_pcode_read_psf_gv_point_info() argument
144 ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in adls_pcode_read_psf_gv_point_info()
157 static u16 icl_qgv_points_mask(struct intel_display *display) in icl_qgv_points_mask() argument
159 unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points; in icl_qgv_points_mask()
160 unsigned int num_qgv_points = display->bw.max[0].num_qgv_points; in icl_qgv_points_mask()
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H A Dintel_hdcp.c17 #include <drm/display/drm_hdcp_helper.h>
49 struct intel_display *display = to_intel_display(encoder); in intel_hdcp_adjust_hdcp_line_rekeying() local
57 if (DISPLAY_VER(display) >= 30) { in intel_hdcp_adjust_hdcp_line_rekeying()
58 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
60 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || in intel_hdcp_adjust_hdcp_line_rekeying()
61 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
62 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
64 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
65 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
70 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); in intel_hdcp_adjust_hdcp_line_rekeying()
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H A Dintel_backlight.c92 struct intel_display *display = to_intel_display(connector); in intel_backlight_invert_pwm_level() local
95 drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0); in intel_backlight_invert_pwm_level()
97 if (display->params.invert_brightness < 0) in intel_backlight_invert_pwm_level()
100 if (display->params.invert_brightness > 0 || in intel_backlight_invert_pwm_level()
101 intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)) { in intel_backlight_invert_pwm_level()
111 struct intel_display *display = to_intel_display(connector); in intel_backlight_set_pwm_level() local
114 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n", in intel_backlight_set_pwm_level()
121 struct intel_display *display = to_intel_display(connector); in intel_backlight_level_to_pwm() local
124 drm_WARN_ON_ONCE(display->drm, in intel_backlight_level_to_pwm()
135 struct intel_display *display = to_intel_display(connector); in intel_backlight_level_from_pwm() local
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H A Dintel_display_rpm.c9 struct ref_tracker *intel_display_rpm_get_raw(struct intel_display *display) in intel_display_rpm_get_raw() argument
11 return display->parent->rpm->get_raw(display->drm); in intel_display_rpm_get_raw()
14 void intel_display_rpm_put_raw(struct intel_display *display, struct ref_tracker *wakeref) in intel_display_rpm_put_raw() argument
16 display->parent->rpm->put_raw(display->drm, wakeref); in intel_display_rpm_put_raw()
19 struct ref_tracker *intel_display_rpm_get(struct intel_display *display) in intel_display_rpm_get() argument
21 return display->parent->rpm->get(display->drm); in intel_display_rpm_get()
24 struct ref_tracker *intel_display_rpm_get_if_in_use(struct intel_display *display) in intel_display_rpm_get_if_in_use() argument
26 return display->parent->rpm->get_if_in_use(display->drm); in intel_display_rpm_get_if_in_use()
29 struct ref_tracker *intel_display_rpm_get_noresume(struct intel_display *display) in intel_display_rpm_get_noresume() argument
31 return display->parent->rpm->get_noresume(display->drm); in intel_display_rpm_get_noresume()
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H A Dintel_crt.c91 bool intel_crt_port_enabled(struct intel_display *display, in intel_crt_port_enabled() argument
96 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
99 if (HAS_PCH_CPT(display)) in intel_crt_port_enabled()
110 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_hw_state() local
115 wakeref = intel_display_power_get_if_enabled(display, in intel_crt_get_hw_state()
120 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
122 intel_display_power_put(display, encoder->power_domain, wakeref); in intel_crt_get_hw_state()
129 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_flags() local
133 tmp = intel_de_read(display, crt->adpa_reg); in intel_crt_get_flags()
178 struct intel_display *display = to_intel_display(encoder); in intel_crt_set_dpms() local
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H A Dintel_dpio_phy.c42 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
43 * ports. DPIO is the name given to such a display PHY. These PHYs
50 * Each display PHY is made up of one or two channels. Each channel
57 * controlled through some dedicated signals from the display
70 * controlled from the display controller side. No DPIO registers
109 * |---------------|---------------| Display PHY
121 * |---------------| Display PHY
225 bxt_get_phy_list(struct intel_display *display, int *count) in bxt_get_phy_list() argument
227 if (display->platform.geminilake) { in bxt_get_phy_list()
237 bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy) in bxt_get_phy_info() argument
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H A Dintel_display.c35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_tunnel.h>
150 /* WA Display #0827: Gen9:all */
152 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) in skl_wa_827() argument
154 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in skl_wa_827()
161 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_scalerclkgating() argument
164 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
171 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, in icl_wa_cursorclkgating() argument
174 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), in icl_wa_cursorclkgating()
343 struct intel_display *display = to_intel_display(crtc_state); in intel_primary_crtc() local
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,imx8qxp-dc-intc.yaml7 title: Freescale i.MX8qxp Display Controller interrupt controller
10 The Display Controller has a built-in interrupt controller with the following
50 (display controller, content stream 0)
53 (display controller, content stream 0)
56 (display controller, content stream 0)
59 (display controller, safety stream 0)
62 (display controller, safety stream 0)
65 (display controller, safety stream 0)
68 (display controller, content stream 1)
71 (display controller, content stream 1)
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