Home
last modified time | relevance | path

Searched full:different (Results 1 – 25 of 4904) sorted by relevance

12345678910>>...197

/linux-5.10/Documentation/process/
Dstable-api-nonsense.rst64 - Depending on the version of the C compiler you use, different kernel
65 data structures will contain different alignment of structures, and
66 possibly include different functions in different ways (putting
68 isn't that important, but the different data structure padding is
72 different things can be assumed by the kernel:
74 - different structures can contain different fields
77 - Memory within the kernel can be aligned in different ways,
80 - Linux runs on a wide range of different processor architectures.
89 different Linux distributions and the number of different supported
91 different build options on different releases. Also realize that each
[all …]
/linux-5.10/tools/testing/selftests/net/forwarding/
Dtc_vlan_modify.sh108 check_fail $? "ping between two different vlans passed when should not"
111 check_fail $? "ping6 between two different vlans passed when should not"
119 check_err $? "ping between two different vlans failed when should not"
122 check_err $? "ping6 between two different vlans failed when should not"
135 check_fail $? "ping between two different vlans passed when should not"
138 check_fail $? "ping6 between two different vlans passed when should not"
146 check_err $? "ping between two different vlans failed when should not"
149 check_err $? "ping6 between two different vlans failed when should not"
Dethtool.sh78 # Test that when we force different speeds, links are not up and ping
92 check_fail $? "ping with different speeds"
94 log_test "force of different speeds autoneg off"
262 # Test that when we configure links to advertise different speeds,
280 check_fail $? "ping with different speeds autoneg on"
283 log_test "advertise different speeds autoneg on"
/linux-5.10/Documentation/powerpc/
Dvcpudispatch_stats.rst11 scenarios, vcpus may be dispatched on a different processor chip (away
33 3. number of times this vcpu was dispatched on a different processor core
35 4. number of times this vcpu was dispatched on a different chip
36 5. number of times this vcpu was dispatches on a different socket/drawer
43 7. number of times this vcpu was dispatched in a different node
69 physical cpu as the last time. 2683 were on a different core, but within
70 the same chip, while 30 dispatches were on a different chip compared to
/linux-5.10/Documentation/admin-guide/namespaces/
Dcompatibility-list.rst6 may have when creating tasks living in different namespaces.
10 in different other namespaces (the rows):
28 other task living in a different namespace via a shared filesystem
33 2. Intentionally, two equal user IDs in different user namespaces
40 from different user namespaces should not access the same IPC objects
/linux-5.10/include/uapi/linux/
Dfalloc.h19 * Different filesystems may implement different limitations on the
51 * Different filesystems may implement different limitations on the granularity
68 * Different filesystems may implement different limitations on the
/linux-5.10/drivers/gpu/drm/msm/
DNOTES3 In the current snapdragon SoC's, we have (at least) 3 different
20 with N different kms devices from xf86-video-freedreno. Plus, it
25 So, the approach is one drm driver, with some modularity. Different
27 And one or more 'struct msm_gpu' for the various different gpu sub-
57 than needing a different implementation for DTV, DSI, etc. (Ie. the
58 register interface is same, just different bases.)
/linux-5.10/Documentation/userspace-api/media/v4l/
Dcolorspaces.rst20 the human eye has color receptors that are sensitive to three different
23 different wavelengths, so instead of RGB we would be using the
34 possible that different SPDs will result in the same stimulation of
36 of the light is different.
68 different wavelengths, the combination of which will stimulate the color
74 Different display devices will have different primaries and some
77 different display technologies or uses. To define a colorspace you need
150 mix of different standards also led to very confusing naming conventions
Dformat.rst13 Different devices exchange different kinds of data with applications,
15 within one kind many different formats are possible, in particular there is an
44 example, when the new standard uses a different number of scan lines,
47 multiple file descriptors which grabbed different logical streams
/linux-5.10/Documentation/virt/
Dparavirt_ops.rst7 Linux provides support for different hypervisor virtualization technologies.
8 Historically different binary kernels would be required in order to support
9 different hypervisors, this restriction was removed with pv_ops.
10 Linux pv_ops is a virtualization API which enables support for different
/linux-5.10/Documentation/devicetree/bindings/sound/
Drt5663.txt23 Based on the different PCB layout, add the manual offset value to
24 compensate the DC offset for each L and R channel, and they are different
38 should compensate different DC offset to avoid the pop sound, and it is
39 also different between headphone and headset. In the example, the
/linux-5.10/tools/testing/ktest/examples/
Dtest.conf8 # BOX can be different than foo, if the machine BOX has
9 # multiple partitions with different systems installed. For example,
12 # machine, which may be different between which system the machine
55 # The following files each handle a different test case.
/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/
Dcache.json5 …e was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
6 …e was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
11 …che was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
12 …che was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
17 …": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (D…
18 …": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (D…
107 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
108 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
Dmarked.json35 …e was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
41 …cles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
47 …che was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
53 …cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
59 …": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (D…
65 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Gr…
251 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
257 …to reload either shared or modified data from another core's L2/L3 on a different chip (remote or …
365 …d into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
371 …ded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
[all …]
Dfrontend.json89 …e was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
90 …e was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
95 …che was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
96 …che was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
101 … processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (D…
102 … processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (D…
203 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
204 … reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or …
293 …d into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (D…
299 …ded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (D…
[all …]
/linux-5.10/Documentation/devicetree/bindings/mailbox/
Domap-mailbox.txt4 The OMAP mailbox hardware facilitates communication between different processors
17 and tx interrupt source per h/w fifo. Communication between different processors
23 instance. DRA7xx has multiple instances with different number of h/w fifo queues
24 and interrupt lines between different instances. The interrupt lines can also be
25 routed to different processor sub-systems on DRA7xx as they are routed through
29 all these clusters are multiplexed and routed to different processor subsystems
78 Each child node should have a unique node name across all the different
/linux-5.10/Documentation/ABI/testing/
Dsysfs-platform-dfl-port7 distinguish different ports under same FPGA device.
13 Description: Read-only. User can program different PR bitstreams to FPGA
14 Accelerator Function Unit (AFU) for different functions. It
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
23 means different throttling level. When reading this file, it
/linux-5.10/tools/memory-model/litmus-tests/
DIRIW+poonceonces+OnceOnce.litmus8 * needed to cause two different reading processes to agree on the order
9 * of a pair of writes, where each write is to a different variable by a
10 * different process?
DIRIW+fencembonceonces+OnceOnce.litmus8 * cause two different reading processes to agree on the order of a pair
9 * of writes, where each write is to a different variable by a different
/linux-5.10/Documentation/admin-guide/mm/
Dconcepts.rst25 address ranges. Besides, different CPU architectures, and even
26 different implementations of the same architecture have different views
103 Often hardware poses restrictions on how different physical memory
115 architectures define all zones, and requirements for DMA are different
116 for different platforms.
123 different access latency depending on the "distance" from the
161 different types of data. It can be kernel internal data structures,
/linux-5.10/tools/testing/selftests/bpf/verifier/
Dunpriv.c219 "unpriv: spill/fill of different pointers stx",
237 .errstr = "same insn cannot be used with different pointers",
241 "unpriv: spill/fill of different pointers stx - ctx and sock",
275 "unpriv: spill/fill of different pointers stx - leak sock",
301 //.errstr = "same insn cannot be used with different pointers",
306 "unpriv: spill/fill of different pointers stx - sock and ctx (read)",
334 .errstr = "same insn cannot be used with different pointers",
338 "unpriv: spill/fill of different pointers stx - sock and ctx (write)",
367 //.errstr = "same insn cannot be used with different pointers",
372 "unpriv: spill/fill of different pointers ldx",
[all …]
/linux-5.10/Documentation/kbuild/
Dreproducible-builds.rst78 generate a different temporary key for each build, resulting in the
114 vDSO's debug information may be identical even for different kernel
116 packages for the different kernel versions.
118 To avoid this, you can make the vDSO different for different
/linux-5.10/Documentation/ABI/
DREADME4 interfaces should be used by userspace programs in different ways.
6 We have four different levels of ABI stability, as shown by the four
7 different subdirectories in this location. Interfaces may change levels
10 The different levels of stability are:
/linux-5.10/arch/x86/include/asm/
Dsync_core.h46 * from the same physical page at a different virtual address.
48 * b) Text was modified on a different CPU, may subsequently be
52 * If you're calling this for a different reason, you're probably doing
104 * in which case we could switch to a different thread in the same mm in sync_core_before_usermode()
/linux-5.10/Documentation/devicetree/bindings/
Dxilinx.txt8 synthesised with different options that change the behaviour.
99 implementations use a different resolution.
139 differ between different families. May be
147 different register spacing and an offset from the base address.
156 The Xilinx USB host controller is EHCI compatible but with a different

12345678910>>...197