Searched full:devices (Results 1 – 10 of 10) sorted by relevance
8 /* These barriers need to enforce ordering on both devices or memory. */13 /* These barriers do not need to enforce ordering on devices, just memory. */
120 new = &its_data.devices[its_data.nr_devices]; in its_create_device()156 if (its_data.devices[i].device_id == id) in its_get_device()157 return &its_data.devices[i]; in its_get_device()
3 * devices exposed from QEMU, e.g. pl011 and chr-testdev. That's5 * devices.
55 struct its_device devices[GITS_MAX_DEVICES]; member56 u32 nr_devices; /* Allocated Devices */
103 /* Header type 0 (normal devices) */305 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */306 #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */307 #define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */308 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */309 #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */310 #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */397 /* PCI-X registers (Type 0 (non-bridge) devices) */437 /* PCI-X registers (Type 1 (bridge) devices) */609 * are only present on devices with PCIe Capability version 2.
4 * devices exposed from QEMU, e.g. ns16550a.
146 /* We ignore I/O channels without valid devices */ in css_enumerate()159 report_info("Tested subchannels: %d, I/O subchannels: %d, I/O devices: %d", in css_enumerate()
230 /* We are only interested in normal PCI devices */ in pci_probe()
474 check = /sys/devices/system/clocksource/clocksource0/current_clocksource=tsc
644 /* There's no guarantee where our devices are without qemu */ in main()