| /linux-5.10/Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
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| D | allwinner,sun4i-a10-system-control.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
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| /linux-5.10/drivers/crypto/ccree/ |
| D | cc_sram_mgr.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
8 * cc_sram_mgr_init() - Initializes SRAM pool.
9 * The pool starts right at the beginning of SRAM.
12 * @drvdata: Associated device driver context
20 struct device *dev = drvdata_to_dev(drvdata); in cc_sram_mgr_init()
22 if (drvdata->hw_rev < CC_HW_REV_712) { in cc_sram_mgr_init()
26 dev_err(dev, "Invalid SRAM offset 0x%x\n", start); in cc_sram_mgr_init()
27 return -EINVAL; in cc_sram_mgr_init()
31 drvdata->sram_free_offset = start; in cc_sram_mgr_init()
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| D | cc_sram_mgr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
13 #define NULL_SRAM_ADDR ((u32)-1)
16 * cc_sram_mgr_init() - Initializes SRAM pool.
17 * The first X bytes of SRAM are reserved for ROM usage, hence, pool
20 * @drvdata: Associated device driver context
28 * cc_sram_alloc() - Allocate buffer from SRAM pool.
30 * @drvdata: Associated device driver context
34 * Address offset in SRAM or NULL_SRAM_ADDR for failure.
39 * cc_set_sram_desc() - Create const descriptors sequence to
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| /linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | cache_sram.txt | 1 * Freescale PQ3 and QorIQ based Cache SRAM
5 as SRAM. This cache SRAM representation in the device
6 tree should be done as under:-
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
|
| /linux-5.10/drivers/soc/sunxi/ |
| D | sunxi_sram.c | 2 * Allwinner SoCs SRAM Controller Driver
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
91 .compatible = "allwinner,sun4i-a10-sram-c1",
95 .compatible = "allwinner,sun4i-a10-sram-d",
99 .compatible = "allwinner,sun50i-a64-sram-c",
105 static struct device *sram_dev;
119 seq_puts(s, "Allwinner sunXi SRAM\n"); in sunxi_sram_show()
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| /linux-5.10/drivers/memory/ |
| D | ti-emif-pm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
39 This driver is for Atmel SDRAM Controller or Atmel Multi-port
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
42 LP-DDR memories.
53 Used to configure the EBI (external bus interface) when the device-
70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
75 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
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| /linux-5.10/arch/arm/mach-omap2/ |
| D | sram.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * OMAP SRAM detection and management
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
28 #include "sram.h"
47 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
55 * SRAM varies. The default accessible size for all device types is 2k. A GP
56 * device allows ARM11 but not other initiators for full size. This
64 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
65 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ in is_sram_locked()
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| /linux-5.10/arch/arm/mach-rockchip/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
52 struct device *dev = get_cpu_device(cpu); in rockchip_get_core_reset()
55 /* The cpu device is only available after the initial core bringup */ in rockchip_get_core_reset()
57 np = dev->of_node; in rockchip_get_core_reset()
92 ret = -1; in pmu_set_power_domain()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
146 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
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| /linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | arm,scmi.txt | 2 ----------------------------------------------------------
11 the device tree.
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
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| D | arm,scpi.txt | 2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 ------------------------------------------------------------
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
38 Sub-nodes
41 - compatible : shall include one of the following
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 3 EMIF - External Memory Interface - is an SDRAM controller used in
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
24 - device-handle : phandle to a "lpddr2" node representing the memory part
26 - ti,hwmods : For TI hwmods processing and omap device creation
29 - interrupts : interrupt used by the controller
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| /linux-5.10/Documentation/devicetree/bindings/net/ |
| D | allwinner,sun4i-a10-emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 EMAC Ethernet Controller Device Tree Bindings
10 - $ref: "ethernet-controller.yaml#"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
18 const: allwinner,sun4i-a10-emac
29 allwinner,sram:
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| /linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
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| /linux-5.10/drivers/net/wireless/intel/iwlegacy/ |
| D | prph.h | 8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
105 * in special SRAM that does not power down when the embedded control
106 * processor is sleeping (e.g. for periodic power-saving shutdowns of radio).
109 * internally loads the short bootstrap program from the special SRAM into the
110 * embedded processor's instruction SRAM, and starts the processor so it runs
119 * The uCode used for open-source drivers includes two programs:
121 * 1) Initialization -- performs hardware calibration and sets up some
128 * 2) Runtime/Protocol -- performs all normal runtime operations. This
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| /linux-5.10/Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-dsp-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
23 Each DSP Core sub-system is represented as a single DT node. Each node has a
25 host processor (Arm CorePac) to perform the device management of the remote
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| D | mtk,scp.txt | 2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be "mediatek,mt8183-scp"
9 - reg Should contain the address ranges for the two memory
10 regions, SRAM and CFG.
11 - reg-names Contains the corresponding names for the two memory
12 regions. These should be named "sram" & "cfg".
13 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
14 - clock-names Contains the corresponding name for the clock. This
18 --------
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| D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 Each Dual-Core R5F sub-system is represented as a single DTS node
24 the device management of the remote processor and to communicate with the
33 - ti,am654-r5fss
34 - ti,j721e-r5fss
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| /linux-5.10/drivers/remoteproc/ |
| D | ti_k3_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017-2020 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
9 #include <linux/dma-mapping.h>
18 #include <linux/omap-mailbox.h>
32 /* R5 TI-SCI Processor Configuration Flags */
42 /* R5 TI-SCI Processor Control Flags */
45 /* R5 TI-SCI Processor Status Flags */
52 * struct k3_r5_mem - internal memory structure
55 * @dev_addr: Device address from remoteproc view
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| /linux-5.10/drivers/misc/ |
| D | sram-exec.c | 2 * SRAM protect-exec region helper functions
4 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
17 #include <linux/device.h>
20 #include <linux/sram.h>
25 #include "sram.h"
30 int sram_check_protect_exec(struct sram_dev *sram, struct sram_reserve *block, in sram_check_protect_exec() argument
33 unsigned long base = (unsigned long)part->base; in sram_check_protect_exec()
34 unsigned long end = base + block->size; in sram_check_protect_exec()
37 dev_err(sram->dev, in sram_check_protect_exec()
38 "SRAM pool marked with 'protect-exec' is not page aligned and will not be created.\n"); in sram_check_protect_exec()
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| /linux-5.10/Documentation/devicetree/bindings/media/ |
| D | allwinner,sun4i-a10-video-engine.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Video Engine Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun4i-a10-video-engine
17 - allwinner,sun5i-a13-video-engine
18 - allwinner,sun7i-a20-video-engine
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| /linux-5.10/arch/powerpc/boot/dts/ |
| D | motionpro.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Motion-PRO board Device Tree Source
11 &gpt0 { fsl,has-wdt; };
12 &gpt6 { // Motion-PRO status LED
13 compatible = "promess,motionpro-led";
14 label = "motionpro-statusled";
15 blink-delay = <100>; // 100 msec
17 &gpt7 { // Motion-PRO ready LED
18 compatible = "promess,motionpro-led";
19 label = "motionpro-readyled";
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| /linux-5.10/Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra186-bpmp.txt | 11 - compatible
14 - "nvidia,tegra186-bpmp"
15 - mboxes : The phandle of mailbox controller and the mailbox specifier.
16 - shmem : List of the phandle of the TX and RX shared memory area that
18 - #clock-cells : Should be 1.
19 - #power-domain-cells : Should be 1.
20 - #reset-cells : Should be 1.
26 - .../mailbox/mailbox.txt
27 - .../mailbox/nvidia,tegra186-hsp.txt
33 - .../clock/clock-bindings.txt
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| /linux-5.10/drivers/fsi/ |
| D | fsi-master-ast-cf.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * A FSI master controller, using a simple GPIO bit-banging interface
9 #include <linux/device.h>
25 #include "fsi-master.h"
26 #include "cf-fsi-fw.h"
28 #define FW_FILE_NAME "cf-fsi-fw.bin"
82 /* Amount of SRAM required */
89 struct device *dev;
111 void __iomem *sram; member
132 msg->msg <<= bits; in msg_push_bits()
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