| /linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | rockchip-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: "synopsys-dw-mshc-common.yaml#"
20 - Heiko Stuebner <heiko@sntech.de>
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
30 - items:
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| D | mmci.txt | 11 - compatible : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - resets : phandle to internal reset line.
20 - vqmmc-supply : phandle to the regulator device tree node, mentioned
23 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
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| /linux-5.10/drivers/mmc/host/ |
| D | dw_mmc-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
29 struct dw_mci_rockchip_priv_data *priv = host->priv; in dw_mci_rk3288_set_ios()
34 if (ios->clock == 0) in dw_mci_rk3288_set_ios()
41 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) in dw_mci_rk3288_set_ios()
44 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
46 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
47 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
48 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; in dw_mci_rk3288_set_ios()
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| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
47 /* Default settings for ZynqMP Clock Phases */
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
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| D | dw_mmc-exynos.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "dw_mmc-pltfm.h"
20 #include "dw_mmc-exynos.h"
22 /* Variations in Exynos specific dw-mshc controller */
52 .compatible = "samsung,exynos4210-dw-mshc",
55 .compatible = "samsung,exynos4412-dw-mshc",
58 .compatible = "samsung,exynos5250-dw-mshc",
61 .compatible = "samsung,exynos5420-dw-mshc",
64 .compatible = "samsung,exynos5420-dw-mshc-smu",
67 .compatible = "samsung,exynos7-dw-mshc",
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| /linux-5.10/Documentation/networking/ |
| D | can.rst | 2 SocketCAN - Controller Area Network
20 .. _socketcan-motivation:
29 functionality. Usually, there is only a hardware-specific device
32 Queueing of frames and higher-level transport protocols like ISO-TP
34 character-device implementations support only one single process to
47 protocol family module and also vice-versa. Also, the protocol family
57 communicate using a specific transport protocol, e.g. ISO-TP, just
60 CAN-IDs, frames, etc.
62 Similar functionality visible from user-space could be provided by a
74 * **Abstraction:** In most existing character-device implementations, the
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| /linux-5.10/drivers/clk/rockchip/ |
| D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
98 return -EINVAL; in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
125 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase()
138 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), in rockchip_mmc_set_phase()
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| /linux-5.10/Documentation/driver-api/media/drivers/ |
| D | cx88-devel.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 -------------------------------------------
13 .. code-block:: none
15 Previous default from DScaler: 0x1c1f0008
16 Digit 8: 31-28
19 Digit 7: 27-24 (0xc = 12 = b1100 )
24 Digits 6,5: 23-16
25 25-16: COMB_RANGE = 0x1f [default] (9 bits -> max 512)
27 Digit 4: 15-12
33 Digit 3: 11-8
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| /linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_audio.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 aud->base.ctx
42 (aud->regs->reg)
46 aud->shifts->field_name, aud->masks->field_name
107 for (index = 0; index < audio_info->mode_count; index++) { in is_audio_format_supported()
108 if (audio_info->modes[index].format_code == audio_format_code) { in is_audio_format_supported()
112 if (audio_info->modes[index].channel_count > in is_audio_format_supported()
113 audio_info->modes[max_channe_index].channel_count) { in is_audio_format_supported()
131 /*For HDMI, calculate if specified sample rates can fit into a given timing */
150 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && in check_audio_bandwidth_hdmi()
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| /linux-5.10/sound/soc/meson/ |
| D | axg-tdm-interface.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <sound/soc-dai.h>
13 #include "axg-tdm.h"
41 dai->playback_dma_data; in axg_tdm_set_tdm_slots()
43 dai->capture_dma_data; in axg_tdm_set_tdm_slots()
52 dev_err(dai->dev, "interface has no slot\n"); in axg_tdm_set_tdm_slots()
53 return -EINVAL; in axg_tdm_set_tdm_slots()
56 iface->slots = slots; in axg_tdm_set_tdm_slots()
75 default: in axg_tdm_set_tdm_slots()
76 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width); in axg_tdm_set_tdm_slots()
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| /linux-5.10/arch/arm64/boot/dts/rockchip/ |
| D | rk3368-lion-haikou.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3368-lion.dtsi"
10 model = "Theobroma Systems RK3368-uQ7 Baseboard";
11 compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368";
14 stdout-path = "serial0:115200n8";
28 pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
30 sd_card_led: led-3 {
33 linux,default-trigger = "mmc0";
37 dc_12v: dc-12v {
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| D | rk3368-px5-evb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
12 compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
15 stdout-path = "serial4:115200n8";
23 keys: gpio-keys {
24 compatible = "gpio-keys";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pwr_key>;
32 wakeup-source;
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| /linux-5.10/arch/arm/boot/dts/ |
| D | rk3288-veyron-sdmmc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 sdcard-supply = <&vccio_sd>;
18 sdmmc_bus4: sdmmc-bus4 {
25 sdmmc_clk: sdmmc-clk {
29 sdmmc_cmd: sdmmc-cmd {
39 sdmmc_cd_disabled: sdmmc-cd-disabled {
44 sdmmc_cd_pin: sdmmc-cd-pin {
51 vcc9-supply = <&vcc_5v>;
55 regulator-name = "vccio_sd";
56 regulator-min-microvolt = <1800000>;
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| /linux-5.10/net/ipv4/ |
| D | tcp_bbr.c | 21 * +---> STARTUP ----+
24 * | DRAIN ----+
27 * +---> PROBE_BW ----+
30 * | +----+ |
32 * +---- PROBE_RTT <--+
37 * A long-lived BBR flow spends the vast majority of its time remaining
41 * sample that matches or decreases its min_rtt estimate for 10 seconds, then
42 * it briefly enters PROBE_RTT to cut inflight to a minimum value to re-probe
43 * the path's two-way propagation delay (min_rtt). When exiting PROBE_RTT, if
48 * "BBR: Congestion-Based Congestion Control",
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| D | tcp_westwood.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TCP Westwood+: end-to-end bandwidth estimation for TCP
10 * - Mascolo S, Casetti, M. Gerla et al.
13 * - A. Grieco, s. Mascolo
17 * - A. Dell'Aera, L. Grieco, S. Mascolo.
18 * "Linux 2.4 Implementation of Westwood+ TCP with Rate-Halving :
21 * Westwood+ employs end-to-end bandwidth measurement to set cwnd and
22 * ssthresh after packet loss. The probing phase is as the original Reno.
43 u8 reset_rtt_min; /* Reset RTT min to next RTT sample*/
65 w->bk = 0; in tcp_westwood_init()
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| D | tcp_veno.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 /* Default values of the Veno variables, in fixed-point representation
36 /* There are several situations when we must "re-start" Veno:
50 veno->doing_veno_now = 1; in veno_enable()
52 veno->minrtt = 0x7fffffff; in veno_enable()
60 veno->doing_veno_now = 0; in veno_disable()
67 veno->basertt = 0x7fffffff; in tcp_veno_init()
68 veno->inc = 1; in tcp_veno_init()
74 const struct ack_sample *sample) in tcp_veno_pkts_acked() argument
79 if (sample->rtt_us < 0) in tcp_veno_pkts_acked()
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| /linux-5.10/tools/perf/Documentation/ |
| D | perf-report.txt | 1 perf-report(1)
5 ----
6 perf-report - Read perf.data (created by perf record) and display the profile
9 --------
11 'perf report' [-i <file> | --input=file]
14 -----------
19 -------
20 -i::
21 --input=::
22 Input file name. (default: perf.data unless stdin is a fifo)
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| D | perf-top.txt | 1 perf-top(1)
5 ----
6 perf-top - System profiling tool.
9 --------
11 'perf top' [-e <EVENT> | --event=EVENT] [<options>]
14 -----------
19 -------
20 -a::
21 --all-cpus::
22 System-wide collection. (default)
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| D | perf-record.txt | 1 perf-record(1)
5 ----
6 perf-record - Run a command and record its profile into perf.data
9 --------
11 'perf record' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf record' [-e <EVENT> | --event=EVENT] [-a] -- <command> [<options>]
15 -----------
17 from it, into perf.data - without displaying anything.
23 -------
27 -e::
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| D | perf-c2c.txt | 1 perf-c2c(1)
5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer.
9 --------
12 'perf c2c record' [<options>] -- [<record command options>] <command>
16 -----------
27 - memory address of the access
28 - type of the access (load and store details)
29 - latency (in cycles) of the load access
32 for cachelines with highest contention - highest number of HITM accesses.
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| /linux-5.10/drivers/gpu/drm/imx/dcss/ |
| D | dcss-scaler.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include "dcss-dev.h"
101 #define PSC_PHASE_MASK (PSC_NUM_PHASES - 1)
103 #define PSC_Q_ROUND_OFFSET (1 << (PSC_Q_FRACTION - 1))
106 * mult_q() - Performs fixed-point multiplication.
122 * div_q() - Performs fixed-point division.
135 temp -= B / 2; in div_q()
142 * exp_approx_q() - Compute approximation to exp(x) function using Taylor
144 * @x: fixed-point argument of exp function
164 * dcss_scaler_gaussian_filter() - Generate gaussian prototype filter.
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| /linux-5.10/include/sound/ |
| D | emu10k1.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
37 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
55 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
57 /* accessed. For non per-channel registers the */
79 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
93 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
106 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
111 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
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| D | cs8427.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
34 #define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
40 #define CS8427_SWCLK (1<<7) /* 0 = RMCK default, 1 = OMCK output on RMCK pin */
52 #define CS8427_HOLDLASTSAMPLE (0<<5) /* hold the last valid sample */
53 #define CS8427_HOLDZERO (1<<5) /* replace the current audio sample with zero (mute) */
54 #define CS8427_HOLDNOCHANGE (2<<5) /* do not change the received audio sample */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
65 #define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
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| /linux-5.10/drivers/media/pci/tw5864/ |
| D | tw5864-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
64 * (Default 0)
71 * 0: Encode (TW5864 Default)
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
99 /* Org Buffer Base for Luma (default 0) */
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| /linux-5.10/drivers/spi/ |
| D | spi-dw-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
16 #include <linux/spi/spi-mem.h>
20 #include "spi-dw.h"
29 u32 rx_sample_dly; /* RX sample delay */
63 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
64 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
65 if (!dws->debugfs) in dw_spi_debugfs_init()
66 return -ENOMEM; in dw_spi_debugfs_init()
68 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
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