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Searched full:ddrpll (Results 1 – 15 of 15) sorted by relevance

/linux-6.8/drivers/clk/zynq/
Dclkc.c50 armpll, ddrpll, iopll, enumerator
239 cpu_parents[2] = clk_output_name[ddrpll]; in zynq_clk_setup()
244 periph_parents[3] = clk_output_name[ddrpll]; in zynq_clk_setup()
265 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
324 clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, in zynq_clk_setup()
330 clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, in zynq_clk_setup()
337 clk_register_divider(NULL, "dci_div0", "ddrpll", 0, in zynq_clk_setup()
/linux-6.8/Documentation/devicetree/bindings/clock/
Dcalxeda.yaml59 ddrpll: ddrpll@108 {
Dzynq-7000.txt42 1: ddrpll
96 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
Dnuvoton,ma35d1-clk.yaml36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
/linux-6.8/drivers/clk/nuvoton/
Dclk-ma35d1-pll.c235 case DDRPLL: in ma35d1_clk_pll_recalc_rate()
267 case DDRPLL: in ma35d1_clk_pll_round_rate()
347 if (id == CAPLL || id == DDRPLL) in ma35d1_reg_clk_pll()
Dclk-ma35d1.c68 { .fw_name = "ddrpll", },
344 { .fw_name = "ddrpll", },
504 hws[DDRPLL] = ma35d1_reg_clk_pll(dev, DDRPLL, pllmode[1], "ddrpll", in ma35d1_clocks_probe()
551 hws[DDR0_GATE] = ma35d1_clk_gate(dev, "ddr0_gate", "ddrpll", in ma35d1_clocks_probe()
553 hws[DDR6_GATE] = ma35d1_clk_gate(dev, "ddr6_gate", "ddrpll", in ma35d1_clocks_probe()
897 hws[DDR_GATE] = ma35d1_clk_gate(dev, "ddr_gate", "ddrpll", in ma35d1_clocks_probe()
/linux-6.8/arch/arm/boot/dts/calxeda/
Decx-common.dtsi145 ddrpll: ddrpll { label
/linux-6.8/drivers/gpu/drm/i915/soc/
Dintel_dram.c86 u16 ddrpll, csipll; in ilk_detect_mem_freq() local
88 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); in ilk_detect_mem_freq()
89 switch (ddrpll & 0xff) { in ilk_detect_mem_freq()
104 ddrpll & 0xff); in ilk_detect_mem_freq()
/linux-6.8/arch/arm64/boot/dts/nuvoton/
Dma35d1-iot-512m.dts42 <&clk DDRPLL>,
Dma35d1-som-256m.dts42 <&clk DDRPLL>,
/linux-6.8/drivers/clk/sifive/
Dfu540-prci.h76 .name = "ddrpll",
Dfu740-prci.h92 .name = "ddrpll",
/linux-6.8/include/dt-bindings/clock/
Dnuvoton,ma35d1-clk.h21 #define DDRPLL 10 macro
/linux-6.8/arch/arm/boot/dts/xilinx/
Dzynq-7000.dtsi320 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",