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/qemu/target/arm/tcg/
H A Dmve_helper.c2 * M-profile MVE Operations
24 #include "exec/helper-proto.h"
25 #include "accel/tcg/cpu-ldst.h"
34 * to beats being executed. The mask has 1 bits for executed lanes in mve_eci_mask()
39 if ((env->condexec_bits & 0xf) != 0) { in mve_eci_mask()
43 eci = env->condexec_bits >> 4; in mve_eci_mask()
66 * (3) low-overhead-branch tail predication will mask out part in mve_element_mask()
70 * We combine all these into a 16-bit result with the same semantics in mve_element_mask()
72 * 8-bit vector ops will look at all bits of the result; in mve_element_mask()
73 * 16-bit ops will look at bits 0, 2, 4, ...; in mve_element_mask()
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H A Dtranslate-neon.c5 * Copyright (c) 2005-2007 CodeSourcery
25 #include "translate-a32.h"
28 #include "decode-neon-dp.c.inc"
29 #include "decode-neon-ls.c.inc"
30 #include "decode-neon-shared.c.inc"
122 int data, gen_helper_gvec_4 *fn_gvec) in do_neon_ddda() argument
124 /* UNDEF accesses to D16-D31 if they don't exist. */ in do_neon_ddda()
131 * Q will be 0b111 for all Q-reg instructions, otherwise in do_neon_ddda()
132 * when we have mixed Q- and D-reg inputs. in do_neon_ddda()
147 opr_sz, opr_sz, data, fn_gvec); in do_neon_ddda()
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H A Dvec_helper.c22 #include "exec/helper-proto.h"
23 #include "tcg/tcg-gvec-desc.h"
30 * Data for expanding active predicate bits to bytes, for byte elements.
132 * Similarly for half-word elements.
157 /* Signed saturating rounding doubling multiply-accumulate high half, 8-bit */
168 ret = -ret; in do_sqrdmlah_b()
221 /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
228 ret = -ret; in do_sqrdmlah_h()
243 uint32_t *sat = &env->vfp.qc[0]; in HELPER()
268 uint32_t *sat = &env->vfp.qc[0]; in HELPER()
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H A Dtranslate-a64.c22 #include "translate-a64.h"
74 #include "decode-sme-fa64.c.inc"
75 #include "decode-a64.c.inc"
112 ARMMMUIdx useridx = s->mmu_idx; in get_a64_user_mem_index()
114 if (unpriv && s->unpriv) { in get_a64_user_mem_index()
116 * We have pre-computed the condition for AccType_UNPRIV. in get_a64_user_mem_index()
144 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ in set_btype()
147 s->btype = -1; in set_btype()
152 if (s->btype != 0) { in reset_btype()
154 s->btype = 0; in reset_btype()
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H A Da64.decode97 ### Data Processing - Immediate
99 # PC-rel addressing
252 NOP 1101 0101 0000 0011 0010 ---- --- 11111
261 CLREX 1101 0101 0000 0011 0011 ---- 010 11111
262 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
265 DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
266 ISB 1101 0101 0000 0011 0011 ---- 110 11111
292 # to hand-decode it.
330 CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
332 CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
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/qemu/target/microblaze/
H A Dtranslate.c5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
23 #include "accel/tcg/cpu-ldst.h"
24 #include "tcg/tcg-op.h"
25 #include "exec/helper-proto.h"
26 #include "exec/helper-gen.h"
28 #include "exec/translation-block.h"
30 #include "qemu/qemu-print.h"
35 #include "exec/helper-info.c.inc"
39 (((src) >> start) & ((1 << (end - start + 1)) - 1))
75 /* Immediate branch-taken destination, or -1 for indirect. */
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/qemu/tcg/
H A Dtcg-op-gvec.c22 #include "tcg/tcg-temp-internal.h"
23 #include "tcg/tcg-op-common.h"
24 #include "tcg/tcg-op-gvec-common.h"
25 #include "tcg/tcg-gvec-desc.h"
26 #include "tcg-has.h"
63 * overlap at compile-time, but the runtime restrictions remain.
96 uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data) in simd_desc() argument
103 * We want to check that 'data' will fit into SIMD_DATA_BITS. in simd_desc()
104 * However, some callers want to treat the data as a signed in simd_desc()
107 * So here we assert only that the data will fit into the in simd_desc()
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/qemu/tcg/arm/
H A Dtcg-target.c.inc74 /* Q4 - Q7 are call-saved, and skipped. */
185 also Just So Happened to do nothing on pre-v6k so that we
241 INSN_VLD1R = 0xf4a00c00, /* VLD1 (single element to all lanes) */
273 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) >> 2;
285 ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
287 if (offset >= -0xfff && offset <= 0xfff) {
291 offset = -offset;
304 ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
306 if (offset >= -0xff && offset <= 0xff) {
310 offset = -offset;
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/qemu/tcg/i386/
H A Dtcg-target.c.inc94 /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save
95 any of them. Therefore only allow xmm0-xmm5 to be allocated. */
189 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);
198 value -= (uintptr_t)tcg_splitwx_to_rx(code_ptr);
235 * TESTQ -> TESTL (uint32_t)
236 * TESTQ -> BT (is_power_of_2)
506 /* Group 1 opcode extensions for 0x80-0x83.
517 /* Group 2 opcode extensions for 0xc0, 0xc1, 0xd0-0xd3. */
540 #define JCC_JMP (-1)
582 /* We should never be asking for both 16 and 64-bit operation. */
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