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/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt50 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
51 ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
62 ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy,
82 exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
83 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
94 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
106 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
120 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
Dmarvell,armada-370-pinctrl.txt27 mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
28 sata1(prsnt), spi1(cs1)
70 spi0(cs1)
80 mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
83 pcie(clkreq0), spi1(cs1)
95 mpp64 64 gpio, spi0(miso), spi0(cs1)
Dmarvell,armada-38x-pinctrl.txt30 mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
39 mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt)
44 mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
73 mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd)
Dmarvell,armada-375-pinctrl.txt16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
51 mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
Dmarvell,armada-98dx3236-pinctrl.txt18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
Dmarvell,armada-39x-pinctrl.txt39 mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs),
45 mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
77 mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd)
/linux-5.10/drivers/ata/
Dpata_ixp4xx_cf.c104 ioaddr->altstatus_addr = data->cs1 + 0x06; in ixp4xx_setup_port()
105 ioaddr->ctl_addr = data->cs1 + 0x06; in ixp4xx_setup_port()
139 struct resource *cs0, *cs1; in ixp4xx_pata_probe() local
146 cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); in ixp4xx_pata_probe()
148 if (!cs0 || !cs1) in ixp4xx_pata_probe()
162 data->cs1 = devm_ioremap(&pdev->dev, cs1->start, 0x1000); in ixp4xx_pata_probe()
164 if (!data->cs0 || !data->cs1) in ixp4xx_pata_probe()
181 ixp4xx_setup_port(ap, data, cs0->start, cs1->start); in ixp4xx_pata_probe()
/linux-5.10/Documentation/ABI/testing/
Dsysfs-class-watchdog98 chip at CS1.
101 from (CS0->CS1, CS1->CS0) to (CS0->CS0,
102 CS1->CS1).
108 For alternate boot mode (booted from CS1 due to wdt2
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ti/
Demif.txt39 - cs1-used : Have this property if CS1 of this EMIF
41 part attached to CS1, it should be the same type as the one on CS0,
66 cs1-used;
/linux-5.10/arch/sh/boards/
Dboard-urquell.c35 * CS1 : SRAM, registers, LAN, PCMCIA
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
/linux-5.10/sound/soc/intel/catpt/
Ddsp.c212 catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); in catpt_dsp_stall()
214 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_stall()
224 catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); in catpt_dsp_reset()
226 return catpt_readl_poll_shim(cdev, CS1, in catpt_dsp_reset()
255 reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; in catpt_dsp_select_lpclock()
288 catpt_updatel_shim(cdev, CS1, mask, val); in catpt_dsp_select_lpclock()
319 catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); in catpt_dsp_set_regs_defaults()
352 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in lpt_dsp_power_down()
380 catpt_updatel_shim(cdev, CS1, in lpt_dsp_power_up()
402 catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), in wpt_dsp_power_down()
[all …]
/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-fsl-lpspi.yaml37 fsl,spi-only-use-cs1-sel:
40 i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
67 fsl,spi-only-use-cs1-sel;
/linux-5.10/drivers/staging/fbtft/
Dfb_agm1264k-fl.c33 #define CS1 gpio.aux[1] macro
119 if (!par->CS1) { in verify_gpios()
121 "Missing info about 'cs1' gpio. Aborting.\n"); in verify_gpios()
147 } else if (strcasecmp(gpio->name, "cs1") == 0) { in request_gpios_match()
149 par->CS1 = gpio->gpio; in request_gpios_match()
196 /* cs1 */ in write_reg8_bus8()
198 gpiod_set_value(par->CS1, 0); in write_reg8_bus8()
202 gpiod_set_value(par->CS1, 1); in write_reg8_bus8()
401 gpiod_set_value(par->CS1, 1); in write_vmem()
/linux-5.10/drivers/watchdog/
Daspeed_wdt.c205 * after booting from the alternate chip at CS1.
207 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
212 * both versions of the SoC. For alternate boot mode (booted from CS1 due to
/linux-5.10/arch/arm/mach-ep93xx/
Dmicro9.c26 * Micro9-High has up to 64MB of 32-bit flash on CS1
27 * Micro9-Mid has up to 64MB of either 32-bit or 16-bit flash on CS1
29 * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
/linux-5.10/arch/arm/mach-s3c/
Dmach-real6410.c283 u32 cs1; in real6410_machine_init() local
302 cs1 = __raw_readl(S3C64XX_SROM_BW) & in real6410_machine_init()
304 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | in real6410_machine_init()
308 __raw_writel(cs1, S3C64XX_SROM_BW); in real6410_machine_init()
Dmach-mini6410.c313 u32 cs1; in mini6410_machine_init() local
333 cs1 = __raw_readl(S3C64XX_SROM_BW) & in mini6410_machine_init()
335 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | in mini6410_machine_init()
339 __raw_writel(cs1, S3C64XX_SROM_BW); in mini6410_machine_init()
/linux-5.10/drivers/bus/
Dimx-weim.c86 05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */ in imx_weim_gpr_setup()
87 033, /* CS0(64M) CS1(64M) CS2(0M) CS3(0M) */ in imx_weim_gpr_setup()
88 0113, /* CS0(64M) CS1(32M) CS2(32M) CS3(0M) */ in imx_weim_gpr_setup()
89 01111, /* CS0(32M) CS1(32M) CS2(32M) CS3(32M) */ in imx_weim_gpr_setup()
/linux-5.10/arch/hexagon/kernel/
Dptrace.c65 membuf_store(&to, regs->cs1); in genregs_get()
113 INEXT(&regs->cs1, cs1); in genregs_set()
Dsignal.c56 err |= __put_user(regs->cs1, &sc->sc_regs.cs1); in setup_sigcontext()
86 err |= __get_user(regs->cs1, &sc->sc_regs.cs1); in restore_sigcontext()
/linux-5.10/arch/sh/include/mach-common/mach/
Dsh7785lcr.h12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
/linux-5.10/drivers/pinctrl/mvebu/
Dpinctrl-armada-370.c79 MPP_FUNCTION(0x4, "spi0", "cs1"),
81 MPP_FUNCTION(0x6, "spi1", "cs1")),
256 MPP_FUNCTION(0x5, "spi0", "cs1")),
296 MPP_FUNCTION(0x1, "dev", "cs1"),
308 MPP_FUNCTION(0x6, "spi1", "cs1")),
356 MPP_FUNCTION(0x2, "spi0", "cs1")),
/linux-5.10/arch/arm/mach-omap2/
Dsram243x.S33 mov r12, r2 @ capture CS1 vs CS0
48 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
49 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
71 cmp r12, #0x1 @ normalize if cs1 based
Dsram242x.S33 mov r12, r2 @ capture CS1 vs CS0
48 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
49 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
71 cmp r12, #0x1 @ normalize if cs1 based
/linux-5.10/drivers/pinctrl/
Dpinctrl-xway.c247 GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
250 GRP_MUX("nand cs1", EBU, pins_nand_cs1),
303 "ebu a25", "ebu cs1",
305 "nand ale", "nand cs1",
320 "ebu a25", "ebu cs1",
322 "nand ale", "nand cs1",
576 GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
579 GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
624 "ebu a25", "ebu cs1",
626 "nand ale", "nand cs1",
[all …]

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