| /linux-6.8/drivers/gpu/drm/i915/gt/ |
| D | intel_migrate.c | 1 // SPDX-License-Identifier: MIT
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehpsdv_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehpsdv_toggle_pdes()
52 d->offset += SZ_2M; in xehpsdv_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehpsdv_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_insert_pte()
71 d->offset += SZ_64K; in xehpsdv_insert_pte()
80 vm->insert_page(vm, px_dma(pt), d->offset, in insert_pte()
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| D | selftest_engine_cs.c | 1 // SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(>->rps.num_waiters); in perf_begin()
30 queue_work(gt->i915->unordered_wq, >->rps.work); in perf_begin()
31 flush_work(>->rps.work); in perf_begin()
38 atomic_dec(>->rps.num_waiters); in perf_end()
41 return igt_flush_test(gt->i915); in perf_end()
46 struct drm_i915_private *i915 = engine->i915; in timestamp_reg()
49 return RING_TIMESTAMP_UDW(engine->mmio_base); in timestamp_reg()
51 return RING_TIMESTAMP(engine->mmio_base); in timestamp_reg()
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| D | selftest_execlists.c | 1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
47 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
58 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
62 return -ETIME; in wait_for_submit()
78 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
84 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
88 if (rq->fence.error != -EIO) { in wait_for_reset()
90 engine->name, in wait_for_reset()
91 rq->fence.context, in wait_for_reset()
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| D | selftest_timeline.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2018 Intel Corporation
29 struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj; in hwsp_page()
32 return sg_page(obj->mm.pages->sgl); in hwsp_page()
39 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES; in hwsp_cacheline()
49 err = i915_gem_object_lock(tl->hwsp_ggtt->obj, &ww); in selftest_tl_pin()
53 if (err == -EDEADLK) { in selftest_tl_pin()
81 tl = xchg(&state->history[idx], tl); in __mock_hwsp_record()
83 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()
96 while (count--) { in __mock_hwsp_timeline()
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| D | selftest_ring_submission.c | 1 // SPDX-License-Identifier: MIT
13 u32 *cs; in create_wally() local
16 obj = i915_gem_object_create_internal(engine->i915, 4096); in create_wally()
20 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in create_wally()
38 cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC); in create_wally()
39 if (IS_ERR(cs)) { in create_wally()
41 return ERR_CAST(cs); in create_wally()
44 if (GRAPHICS_VER(engine->i915) >= 6) { in create_wally()
45 *cs++ = MI_STORE_DWORD_IMM_GEN4; in create_wally()
46 *cs++ = 0; in create_wally()
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| D | selftest_rc6.c | 1 // SPDX-License-Identifier: MIT
34 struct intel_rc6 *rc6 = >->rc6; in live_rc6_manual()
47 if (!rc6->enabled) in live_rc6_manual()
51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
54 has_power = librapl_supported(gt->i915); in live_rc6_manual()
55 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
66 rc0_power = librapl_energy_uJ() - rc0_power; in live_rc6_manual()
69 if ((res[1] - res[0]) >> 10) { in live_rc6_manual()
71 (res[1] - res[0]) >> 10); in live_rc6_manual()
72 err = -EINVAL; in live_rc6_manual()
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| D | selftest_workarounds.c | 1 // SPDX-License-Identifier: MIT
42 err = -EIO; in request_add_sync()
55 err = -ETIMEDOUT; in request_add_spin()
69 wa_init_start(&lists->gt_wa_list, gt, "GT_REF", "global"); in reference_lists_init()
70 gt_init_workarounds(gt, &lists->gt_wa_list); in reference_lists_init()
71 wa_init_finish(&lists->gt_wa_list); in reference_lists_init()
74 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
76 wa_init_start(wal, gt, "REF", engine->name); in reference_lists_init()
81 &lists->engine[id].ctx_wa_list, in reference_lists_init()
93 intel_wa_list_free(&lists->engine[id].wa_list); in reference_lists_fini()
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| D | selftest_engine_pm.c | 1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
36 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
40 *cs++ = value; in emit_wait()
41 *cs++ = offset; in emit_wait()
42 *cs++ = 0; in emit_wait()
44 return cs; in emit_wait()
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
49 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; in emit_store()
[all …]
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| /linux-6.8/drivers/accel/habanalabs/common/ |
| D | command_submission.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
23 * enum hl_cs_wait_status - cs wait status
24 * @CS_WAIT_STATUS_BUSY: cs was not completed yet
25 * @CS_WAIT_STATUS_COMPLETED: cs completed
26 * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
65 * CS outcome store supports the following operations: in hl_push_cs_outcome()
66 * push outcome - store a recent CS outcome in the store in hl_push_cs_outcome()
67 * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store in hl_push_cs_outcome()
69 * It has a pre-allocated amount of nodes, each node stores in hl_push_cs_outcome()
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| D | hw_queue.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
13 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
23 ptr &= ((HL_QUEUE_LENGTH << 1) - 1); in hl_hw_queue_add_ptr()
28 return atomic_read(ci) & ((queue_len << 1) - 1); in queue_ci_get()
33 int delta = (q->pi - queue_ci_get(&q->ci, queue_len)); in queue_free_slots()
36 return (queue_len - delta); in queue_free_slots()
38 return (abs(delta) - queue_len); in queue_free_slots()
41 void hl_hw_queue_update_ci(struct hl_cs *cs) in hl_hw_queue_update_ci() argument
43 struct hl_device *hdev = cs->ctx->hdev; in hl_hw_queue_update_ci()
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| /linux-6.8/drivers/gpu/drm/i915/selftests/ |
| D | i915_perf.c | 2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strscpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
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| D | i915_request.c | 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
75 request = mock_request(rcs0(i915)->kernel_context, HZ / 10); in igt_add_request()
77 return -ENOMEM; in igt_add_request()
89 int err = -EINVAL; in igt_wait_request()
93 request = mock_request(rcs0(i915)->kernel_context, T); in igt_wait_request()
95 return -ENOMEM; in igt_wait_request()
99 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
104 if (i915_request_wait(request, 0, T) != -ETIME) { in igt_wait_request()
116 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
126 if (i915_request_wait(request, 0, T / 2) != -ETIME) { in igt_wait_request()
[all …]
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| /linux-6.8/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
[all …]
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| /linux-6.8/drivers/spi/ |
| D | spi-omap2-mcspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
151 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
158 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
164 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
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| D | spi-fsl-espi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
39 /* eSPI Controller CS mode register definitions */
118 return ioread32be(espi->reg_base + offset); in fsl_espi_read_reg()
123 return ioread16be(espi->reg_base + offset); in fsl_espi_read_reg16()
128 return ioread8(espi->reg_base + offset); in fsl_espi_read_reg8()
134 iowrite32be(val, espi->reg_base + offset); in fsl_espi_write_reg()
140 iowrite16be(val, espi->reg_base + offset); in fsl_espi_write_reg16()
146 iowrite8(val, espi->reg_base + offset); in fsl_espi_write_reg8()
151 struct fsl_espi *espi = spi_controller_get_devdata(m->spi->controller); in fsl_espi_check_message()
154 if (m->frame_length > SPCOM_TRANLEN_MAX) { in fsl_espi_check_message()
[all …]
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| /linux-6.8/tools/testing/selftests/cachestat/ |
| D | test_cachestat.c | 1 // SPDX-License-Identifier: GPL-2.0
27 void print_cachestat(struct cachestat *cs) in print_cachestat() argument
31 cs->nr_cache, cs->nr_dirty, cs->nr_writeback, in print_cachestat()
32 cs->nr_evicted, cs->nr_recently_evicted); in print_cachestat()
45 goto out; in write_exactly()
67 remained -= read_len; in write_exactly()
83 remained -= write_len; in write_exactly()
92 out: in write_exactly()
125 struct cachestat cs; in test_cachestat() local
130 if (fd == -1) { in test_cachestat()
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| /linux-6.8/kernel/cgroup/ |
| D | cpuset.c | 7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
54 * node binding, add this key to provide a quick low-cost judgment
102 * The user-configured masks can only be changed by writing to
116 * The user-configured masks are always the same with effective masks.
119 /* user-configured CPUs and Memory Nodes allow to tasks */
136 * effective_xcpus may be distributed to sub-partitions below & hence
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| /linux-6.8/drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
176 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
177 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
178 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
179 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
188 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
212 u32 *cs; in restore_context_mmio_for_inhibit() local
215 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
216 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
[all …]
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| /linux-6.8/drivers/gpu/drm/xe/ |
| D | xe_gsc_submit.c | 1 // SPDX-License-Identifier: MIT
42 * xe_gsc_emit_header - write the MTL GSC header in memory
72 * xe_gsc_check_and_update_pending - check the pending bit and update the input
77 * @out: the iosys map containing the output buffer
84 struct iosys_map *out, u32 offset_out) in xe_gsc_check_and_update_pending() argument
86 if (mtl_gsc_header_rd(xe, out, offset_out, flags) & GSC_OUTFLAG_MSG_PENDING) { in xe_gsc_check_and_update_pending()
87 u64 handle = mtl_gsc_header_rd(xe, out, offset_out, gsc_message_handle); in xe_gsc_check_and_update_pending()
98 * xe_gsc_read_out_header - reads and validates the output header and returns
106 * Returns: -errno value on failure, 0 otherwise
115 u32 payload_size = size - GSC_HDR_SIZE; in xe_gsc_read_out_header()
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| /linux-6.8/drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_client_blt.c | 1 // SPDX-License-Identifier: MIT
56 * F so we can use the Y-tile algorithm to get to that point. in linear_x_y_to_ftiled_pos()
66 /* And figure out the subtile within the 4k tile */ in linear_x_y_to_ftiled_pos()
86 CLIENT_TILING_Y, /* Y-major, either Tile4 (Xe_HP and beyond) or legacy TileY */
114 /* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */ in fastblit_supports_x_tiling()
115 drm_WARN_ON(&i915->drm, gen < 9); in fastblit_supports_x_tiling()
128 /* XY_FAST_COPY_BLT does not exist on pre-gen9 platforms */ in fast_blit_ok()
129 if (GRAPHICS_VER(buf->vma->vm->i915) < 9) in fast_blit_ok()
132 /* filter out platforms with unsupported X-tile support in fastblit */ in fast_blit_ok()
133 if (buf->tiling == CLIENT_TILING_X && !fastblit_supports_x_tiling(buf->vma->vm->i915)) in fast_blit_ok()
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| D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
33 goto out; in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
47 i915_gem_object_finish_access(ctx->obj); in cpu_set()
49 out: in cpu_set()
50 i915_gem_object_unlock(ctx->obj); in cpu_set()
61 i915_gem_object_lock(ctx->obj, NULL); in cpu_get()
62 err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); in cpu_get()
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| /linux-6.8/arch/arm64/boot/dts/hisilicon/ |
| D | hi6220-coresight.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
44 in-ports {
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| /linux-6.8/fs/xfs/scrub/ |
| D | stats.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
20 /* all 32-bit counters here */
37 /* all 64-bit items here */
43 /* non-counter state must go at the end for clearall */
85 struct xchk_stats *cs, in xchk_stats_format() argument
89 struct xchk_scrub_stats *css = &cs->cs_stats[0]; in xchk_stats_format()
101 (unsigned int)css->invocations, in xchk_stats_format()
102 (unsigned int)css->clean, in xchk_stats_format()
103 (unsigned int)css->corrupt, in xchk_stats_format()
104 (unsigned int)css->preen, in xchk_stats_format()
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| /linux-6.8/scripts/kconfig/ |
| D | confdata.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>
99 tmp[sizeof(tmp) - 1] = 0; in make_parent_dir()
117 return -1; in make_parent_dir()
137 return -1; in conf_touch_dep()
142 if (fd == -1) in conf_touch_dep()
143 return -1; in conf_touch_dep()
237 switch (sym->type) { in conf_set_sym_val()
240 sym->def[def].tri = mod; in conf_set_sym_val()
241 sym->flags |= def_flags; in conf_set_sym_val()
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| /linux-6.8/tools/perf/util/ |
| D | data-convert-bt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <babeltrace/ctf-writer/writer.h>
15 #include <babeltrace/ctf-writer/clock.h>
16 #include <babeltrace/ctf-writer/stream.h>
17 #include <babeltrace/ctf-writer/event.h>
18 #include <babeltrace/ctf-writer/event-types.h>
19 #include <babeltrace/ctf-writer/event-fields.h>
20 #include <babeltrace/ctf-ir/utils.h>
23 #include "data-convert.h"
39 #include <traceevent/event-parse.h>
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