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Searched full:cpu_clk (Results 1 – 25 of 72) sorted by relevance

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/linux-5.10/drivers/cpufreq/
Dtegra124-cpufreq.c21 struct clk *cpu_clk; member
33 ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk)); in tegra124_cpu_switch_to_dfll()
37 orig_parent = clk_get_parent(priv->cpu_clk); in tegra124_cpu_switch_to_dfll()
38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
44 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll()
49 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll()
74 priv->cpu_clk = of_clk_get_by_name(np, "cpu_g"); in tegra124_cpufreq_probe()
75 if (IS_ERR(priv->cpu_clk)) { in tegra124_cpufreq_probe()
76 ret = PTR_ERR(priv->cpu_clk); in tegra124_cpufreq_probe()
125 clk_put(priv->cpu_clk); in tegra124_cpufreq_probe()
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Dmediatek-cpufreq.c40 struct clk *cpu_clk; member
206 struct clk *cpu_clk = policy->clk; in mtk_cpufreq_set_target() local
207 struct clk *armpll = clk_get_parent(cpu_clk); in mtk_cpufreq_set_target()
216 old_freq_hz = clk_get_rate(cpu_clk); in mtk_cpufreq_set_target()
250 ret = clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
264 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
270 ret = clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
288 clk_set_parent(cpu_clk, info->inter_clk); in mtk_cpufreq_set_target()
290 clk_set_parent(cpu_clk, armpll); in mtk_cpufreq_set_target()
305 struct clk *cpu_clk = ERR_PTR(-ENODEV); in mtk_cpu_dvfs_info_init() local
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Dkirkwood-cpufreq.c21 struct clk *cpu_clk; member
65 clk_set_parent(priv.powersave_clk, priv.cpu_clk); in kirkwood_cpufreq_target()
119 priv.cpu_clk = of_clk_get_by_name(np, "cpu_clk"); in kirkwood_cpufreq_probe()
120 if (IS_ERR(priv.cpu_clk)) { in kirkwood_cpufreq_probe()
122 err = PTR_ERR(priv.cpu_clk); in kirkwood_cpufreq_probe()
126 err = clk_prepare_enable(priv.cpu_clk); in kirkwood_cpufreq_probe()
132 kirkwood_freq_table[0].frequency = clk_get_rate(priv.cpu_clk) / 1000; in kirkwood_cpufreq_probe()
174 clk_disable_unprepare(priv.cpu_clk); in kirkwood_cpufreq_probe()
187 clk_disable_unprepare(priv.cpu_clk); in kirkwood_cpufreq_remove()
Dtango-cpufreq.c16 struct clk *cpu_clk; in tango_cpufreq_init() local
22 cpu_clk = clk_get(cpu_dev, NULL); in tango_cpufreq_init()
23 if (IS_ERR(cpu_clk)) in tango_cpufreq_init()
26 max_freq = clk_get_rate(cpu_clk); in tango_cpufreq_init()
Dhighbank-cpufreq.c62 struct clk *cpu_clk; in hb_cpufreq_driver_init() local
82 cpu_clk = clk_get(cpu_dev, NULL); in hb_cpufreq_driver_init()
83 if (IS_ERR(cpu_clk)) { in hb_cpufreq_driver_init()
84 ret = PTR_ERR(cpu_clk); in hb_cpufreq_driver_init()
89 ret = clk_notifier_register(cpu_clk, &hb_cpufreq_clk_nb); in hb_cpufreq_driver_init()
Dcpufreq-dt.c108 struct clk *cpu_clk; in cpufreq_init() local
121 cpu_clk = clk_get(cpu_dev, NULL); in cpufreq_init()
122 if (IS_ERR(cpu_clk)) { in cpufreq_init()
123 ret = PTR_ERR(cpu_clk); in cpufreq_init()
159 policy->clk = cpu_clk; in cpufreq_init()
189 clk_put(cpu_clk); in cpufreq_init()
/linux-5.10/arch/mips/ar7/
Dtime.c19 struct clk *cpu_clk; in plat_time_init() local
24 cpu_clk = clk_get(NULL, "cpu"); in plat_time_init()
25 if (IS_ERR(cpu_clk)) { in plat_time_init()
30 mips_hpt_frequency = clk_get_rate(cpu_clk) / 2; in plat_time_init()
Dclock.c91 static struct clk cpu_clk = { variable
182 base_clock = cpu_clk.rate; in tnetd7300_get_clock()
222 base_clock = cpu_clk.rate; in tnetd7300_set_clock()
248 cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
251 cpu_clk.rate = bus_clk.rate; in tnetd7300_init_clocks()
349 cpu_clk.rate = in tnetd7200_init_clocks()
353 cpu_clk.rate); in tnetd7200_init_clocks()
362 cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul) in tnetd7200_init_clocks()
366 cpu_clk.rate); in tnetd7200_init_clocks()
371 bus_clk.rate = cpu_clk.rate / 2; in tnetd7200_init_clocks()
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/linux-5.10/arch/arm/mach-mvebu/
Dplatsmp.c42 struct clk *cpu_clk; in get_cpu_clk() local
47 cpu_clk = of_clk_get(np, 0); in get_cpu_clk()
48 if (WARN_ON(IS_ERR(cpu_clk))) in get_cpu_clk()
50 return cpu_clk; in get_cpu_clk()
104 struct clk *cpu_clk = get_cpu_clk(cpu); in armada_xp_sync_secondary_clk() local
106 if (!cpu_clk || !boot_cpu_clk) in armada_xp_sync_secondary_clk()
109 clk_prepare_enable(cpu_clk); in armada_xp_sync_secondary_clk()
110 clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk)); in armada_xp_sync_secondary_clk()
/linux-5.10/arch/sh/kernel/cpu/
Dclock-cpg.c24 static struct clk cpu_clk = { variable
36 &cpu_clk,
44 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
/linux-5.10/Documentation/devicetree/bindings/arm/marvell/
Dkirkwood.txt12 cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
14 between the "cpu_clk" and the "ddrclk".
26 clock-names = "cpu_clk", "ddrclk", "powersave";
/linux-5.10/arch/mips/lantiq/xway/
Dclk.c144 unsigned int ocp_sel, cpu_clk; in ltq_vr9_fpi_hz() local
147 cpu_clk = ltq_vr9_cpu_hz(); in ltq_vr9_fpi_hz()
153 clk = cpu_clk; in ltq_vr9_fpi_hz()
157 clk = cpu_clk / 2; in ltq_vr9_fpi_hz()
161 clk = (cpu_clk * 2) / 5; in ltq_vr9_fpi_hz()
165 clk = cpu_clk / 3; in ltq_vr9_fpi_hz()
/linux-5.10/drivers/clk/mvebu/
Dclk-cpu.c33 struct cpu_clk { struct
46 #define to_cpu_clk(p) container_of(p, struct cpu_clk, hw) argument
51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_recalc_rate()
78 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_off_set_rate()
113 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_on_set_rate()
168 struct cpu_clk *cpuclk; in of_cpu_clk_setup()
/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap806-quad.dtsi24 clocks = <&cpu_clk 0>;
39 clocks = <&cpu_clk 0>;
54 clocks = <&cpu_clk 1>;
69 clocks = <&cpu_clk 1>;
Darmada-ap807-quad.dtsi24 clocks = <&cpu_clk 0>;
39 clocks = <&cpu_clk 0>;
54 clocks = <&cpu_clk 1>;
69 clocks = <&cpu_clk 1>;
Darmada-ap806-dual.dtsi24 clocks = <&cpu_clk 0>;
39 clocks = <&cpu_clk 0>;
Darmada-ap807.dtsi24 cpu_clk: clock-cpu { label
/linux-5.10/arch/arc/boot/dts/
Dabilis_tb10x.dtsi31 clocks = <&cpu_clk>;
37 clocks = <&cpu_clk>;
53 cpu_clk: clkdiv_cpu { label
57 clock-output-names = "cpu_clk";
/linux-5.10/drivers/clk/loongson1/
Dclk-loongson1c.c60 hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div", in ls1x_clk_init()
62 clk_hw_register_clkdev(hw, "cpu_clk", NULL); in ls1x_clk_init()
Dclk-loongson1b.c65 hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents, in ls1x_clk_init()
69 clk_hw_register_clkdev(hw, "cpu_clk", NULL); in ls1x_clk_init()
/linux-5.10/drivers/base/
Darch_topology.c168 struct clk *cpu_clk; in topology_parse_cpu_capacity() local
198 cpu_clk = of_clk_get(cpu_node, 0); in topology_parse_cpu_capacity()
199 if (!PTR_ERR_OR_ZERO(cpu_clk)) { in topology_parse_cpu_capacity()
201 clk_get_rate(cpu_clk) / 1000; in topology_parse_cpu_capacity()
202 clk_put(cpu_clk); in topology_parse_cpu_capacity()
/linux-5.10/arch/mips/boot/dts/mscc/
Docelot.dtsi16 clocks = <&cpu_clk>;
32 cpu_clk: cpu-clock { label
41 clocks = <&cpu_clk>;
/linux-5.10/drivers/clk/
Dclk-tango4.c8 #define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
73 pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0, in tango4_clkgen_setup()
/linux-5.10/arch/arm/boot/dts/
Dtango4-common.dtsi9 #define CPU_CLK 0 macro
21 clocks = <&clkgen CPU_CLK>;
/linux-5.10/drivers/clk/sunxi-ng/
Dccu-suniv-f1c100s.c109 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
319 &cpu_clk.common,
410 [CLK_CPU] = &cpu_clk.common.hw,
519 .common = &cpu_clk.common,
520 .cm = &cpu_clk.mux,

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