| /linux-6.8/drivers/pci/controller/ |
| D | pcie-iproc-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include "pcie-iproc.h"
52 * struct iproc_msi_grp - iProc MSI group
68 * struct iproc_msi - iProc event queue based MSI
73 * @pcie: pointer to iProc PCIe data
94 struct iproc_pcie *pcie; member
132 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_read_reg() local
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
141 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_write_reg() local
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
[all …]
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| /linux-6.8/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-io.json | 12 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
27 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
41 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
51 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
61 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
71 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
81 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
91 "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
101 "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
111 "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-io.json | 12 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
27 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
41 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
51 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
61 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
71 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
81 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
91 "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
101 "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
111 "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| D | uncore-io.json | 84 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
90 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
95 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
101 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card …
106 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
112 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card …
117 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
123 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card …
128 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
134 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card …
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | uncore-io.json | 148 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
154 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
159 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
165 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card …
170 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
176 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card …
181 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
187 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card …
192 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
198 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card …
[all …]
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| /linux-6.8/Documentation/admin-guide/perf/ |
| D | nvidia-pmu.rst | 9 * NVLink-C2C0
10 * NVLink-C2C1
12 * PCIE
15 ----------
19 PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
22 the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
29 -------
31 The SCF PMU monitors system level cache events, CPU traffic, and
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
37 see /sys/bus/event_sources/devices/nvidia_scf_pmu_<socket-id>.
[all …]
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| /linux-6.8/arch/arm/boot/dts/marvell/ |
| D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,sheeva-v7";
[all …]
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| D | armada-385.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
23 cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a9";
[all …]
|
| D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "marvell,sheeva-v7";
[all …]
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| /linux-6.8/arch/arm64/boot/dts/marvell/ |
| D | ac5x-rd-carrier-cn9131.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Utilizing the CN913x COM Express CPU module board.
8 * only maintains a PCIe link with the CPU module,
13 * which would allow it to use an external CN9131 CPU COM Express module,
19 * When the board boots in the external CPU mode, the internal CPU is disabled,
20 * and only the switch portion of the SOC acts as a PCIe end-point, Hence there
21 * is no need to describe this internal (disabled CPU) in the device tree.
23 * There is no CPU booting in this mode on the carrier, only on the
24 * CN9131 COM Express CPU module.
25 * What runs the Linux is the CN9131 on the COM Express CPU module,
[all …]
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| /linux-6.8/arch/arm64/boot/dts/amlogic/ |
| D | meson-sm1-khadas-vim3l.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1.dtsi"
10 #include "meson-khadas-vim3.dtsi"
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
17 vddcpu: regulator-vddcpu {
21 compatible = "pwm-regulator";
23 regulator-name = "VDDCPU";
24 regulator-min-microvolt = <690000>;
25 regulator-max-microvolt = <1050000>;
[all …]
|
| /linux-6.8/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls2088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
15 &cpu {
16 cpu0: cpu@0 {
17 device_type = "cpu";
18 compatible = "arm,cortex-a72";
21 cpu-idle-states = <&CPU_PW20>;
22 next-level-cache = <&cluster0_l2>;
[all …]
|
| /linux-6.8/arch/arm/boot/dts/airoha/ |
| D | en7523.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
13 reserved-memory {
14 #address-cells = <1>;
[all …]
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| /linux-6.8/arch/mips/boot/dts/ralink/ |
| D | mt7621.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "mediatek,mt7621-soc";
13 #address-cells = <1>;
14 #size-cells = <0>;
[all …]
|
| /linux-6.8/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
31 USB, UFS, SD/eMMC, PCIe, etc.
37 the CPU with frequencies above 1GHz.
38 Say Y if you want to support higher CPU frequencies on MSM8916
44 Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with
46 Say Y if you want to support higher CPU frequencies on SDX55 and SDX65
55 Say Y if you want to support CPU frequency scaling on devices
59 tristate "MSM8996 CPU Clock Controller"
64 Support for the CPU clock controller on msm8996 devices.
65 Say Y if you want to support CPU clock scaling using CPUfreq
[all …]
|
| /linux-6.8/arch/powerpc/boot/dts/fsl/ |
| D | p3041si-post.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
|
| D | p4080si-post.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
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| D | t1040si-post.dtsi | 4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
|
| /linux-6.8/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCIe Endpoint Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sdx55-pcie-ep
17 - qcom,sm8450-pcie-ep
18 - items:
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | uncore-io.json | 84 "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
94 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
100 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
105 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
111 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card …
116 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
122 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card …
127 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
133 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card …
138 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
[all …]
|
| /linux-6.8/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | uncore-io.json | 12 …"PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes)…
27 …"PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) t…
113 "BriefDescription": "PCIe Completion Buffer Inserts : All Ports",
123 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
129 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
134 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
140 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card …
145 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
151 …"PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card …
156 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
[all …]
|
| /linux-6.8/arch/arm/boot/dts/nxp/imx/ |
| D | imx7d.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
17 cpu0: cpu@0 {
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
25 cpu1: cpu@1 {
26 compatible = "arm,cortex-a7";
[all …]
|
| /linux-6.8/arch/loongarch/boot/dts/ |
| D | loongson-2k2000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu0: cpu@1 {
20 device_type = "cpu";
25 cpu1: cpu@2 {
[all …]
|
| /linux-6.8/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include "pcie-cadence.h"
11 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
19 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
24 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
27 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
35 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
47 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
[all …]
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| /linux-6.8/drivers/pci/controller/dwc/ |
| D | pcie-visconti.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
96 /* Access registers in PCIe ulreg */
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
107 /* Access registers in PCIe smu */
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
[all …]
|