Searched full:coprocessor (Results 1 – 25 of 211) sorted by relevance
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14 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing P…21 …nctions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy perform…28 …s blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy perform…42 …"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the S…49 …A functions that are issued by the CPU and are blocked because the SHA coprocessor is busy perform…56 …cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy perform…70 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…77 …nctions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy perform…84 …es blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy perform…98 …"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing t…[all …]
14 …"PublicDescription": "This counter counts the total number of CPU cycles when the ECC coprocessor …21 …) functions that are issued by the CPU and are blocked because the ECC coprocessor is busy perform…28 …c-curve cryptography (ECC) functions issued by the CPU because the ECC coprocessor is busy perform…
7 * This provides the Initiate Coprocessor Store Word Indexed (ICSWX)10 * to communicate with the coprocessor.12 * The RFC02130: Coprocessor Architecture document is the reference for20 /* Chapter 6.5.8 Coprocessor-Completion Block (CCB) */42 /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */125 /* Chapter 6.5.2 Coprocessor-Request Block (CRB) */130 /* Coprocessor Status Block field161 /* RFC02167 Initiate Coprocessor Instructions document163 * Chapter 8.2.3 Coprocessor Directive175 /* RFC02167 Initiate Coprocessor Instructions document[all …]
5 * XScale DSP and iWMMXt coprocessor context switching and handling114 * Detect whether we have a MAC coprocessor (40 bit register) or an115 * iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000116 * into a coprocessor register and reading it back, and checking125 * This sequence is interpreted by the DSP coprocessor as: in cpu_has_iwmmxt()129 * And by the iWMMXt coprocessor as: in cpu_has_iwmmxt()147 * hand the CPU has a DSP coprocessor, we keep access to CP0 enabled164 pr_warn("CAUTION: XScale iWMMXt coprocessor detected, but kernel support is missing.\n"); in xscale_cp0_init()166 pr_info("XScale iWMMXt coprocessor detected.\n"); in xscale_cp0_init()171 pr_info("XScale DSP coprocessor detected.\n"); in xscale_cp0_init()
5 * PJ4 iWMMXt coprocessor context switching and handling83 /* check if coprocessor 0 and 1 are available */ in pj4_get_iwmmxt_version()89 /* read iWMMXt coprocessor id register p1, c0 */ in pj4_get_iwmmxt_version()121 pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n"); in pj4_cp0_init()126 pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers); in pj4_cp0_init()
2 * arch/xtensa/kernel/coprocessor.S4 * Xtensa processor configuration-specific table of coprocessor and18 #include <asm/coprocessor.h>106 * Save coprocessor registers for coprocessor 'index'.107 * The register values are saved to or loaded from the coprocessor area 167 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */190 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */203 addx8 a3, a3, a5 # a3: coprocessor number
80 #define COPROCESSOR(x) \ macro128 COPROCESSOR(0),131 COPROCESSOR(1),134 COPROCESSOR(2),137 COPROCESSOR(3),140 COPROCESSOR(4),143 COPROCESSOR(5),146 COPROCESSOR(6),149 COPROCESSOR(7),
66 "Coprocessor 0 instruction when cp0 disabled"},68 "Coprocessor 1 instruction when cp1 disabled"},70 "Coprocessor 2 instruction when cp2 disabled"},72 "Coprocessor 3 instruction when cp3 disabled"},74 "Coprocessor 4 instruction when cp4 disabled"},76 "Coprocessor 5 instruction when cp5 disabled"},78 "Coprocessor 6 instruction when cp6 disabled"},80 "Coprocessor 7 instruction when cp7 disabled"},
14 /* Chapter 6.5.8 Coprocessor-Completion Block (CCB) */36 /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */103 /* Chapter 6.5.2 Coprocessor-Request Block (CRB) */109 /* Coprocessor Status Block field142 /* RFC02167 Initiate Coprocessor Instructions document144 * Chapter 8.2.3 Coprocessor Directive
11 * restored. Coprocessor registers are stored in uc_regspace. Each12 * coprocessor's saved state should start with a documented 32-bit magic34 * Coprocessor save state. The magic values and specific35 * coprocessor's layouts are part of the userspace ABI. Each one of104 /* Something that isn't a valid magic number for any coprocessor. */
2 menu "ACP (Audio CoProcessor) Configuration"6 bool "Enable AMD Audio CoProcessor IP support"12 This adds the ACP (Audio CoProcessor) IP driver and wires
5 DAX is a coprocessor which resides on the SPARC M7 (DAX1) and M812 into the driver and subsequently the Hypervisor and the coprocessor.14 coprocessor, and the driver interface is not intended for general use.24 The Hypervisor interface to the coprocessor is described in detail in33 A coprocessor request is described by a Command Control Block38 requests to the available coprocessor execution units. A status code42 is written by the coprocessor to provide execution status. No47 coprocessor. This is done using the monitored load and mwait49 coprocessor was designed so that after a request is submitted, the69 The DAX coprocessor can only operate on physical memory, so before a[all …]
12 Chapter 36. Coprocessor services44 …The availablility of DAX coprocessor command service is indicated by the presence of the DAX virtu…66 Coprocessor services122 36.2. Coprocessor Control Block (CCB)128 Coprocessor services176 Coprocessor services228 Coprocessor services284 Coprocessor services342 Coprocessor services397 Coprocessor services[all …]
18 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */19 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */32 /* Macro to save all non-coprocessor (extra) custom TIE and optional state47 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
1 * ASPEED AST2400 and AST2500 coprocessor interrupt controller5 ColdFire coprocessor.25 SW interrupts from the ARM to the coprocessor.
3 tristate "AMD Audio Coprocessor support"25 tristate "AMD Audio Coprocessor-v3.x support"42 tristate "AMD Audio Coprocessor - Renoir support"
46 unsigned int ci; /* Coprocessor instance, used with icswx */65 * Using same values as in skiboot or coprocessor type representing346 CSB_ERR_ADDR(csb, "Read error outside coprocessor"); in wait_for_csb()349 CSB_ERR_ADDR(csb, "Write error outside coprocessor"); in wait_for_csb()352 CSB_ERR(csb, "Internal error in coprocessor"); in wait_for_csb()428 * (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.473 pr_err_ratelimited("coprocessor CT is 0"); in nx842_exec_icswx()500 * NX842 coprocessor sets 3rd bit in CR register with XER[S0]. in nx842_exec_icswx()512 pr_debug_ratelimited("842 Coprocessor busy\n"); in nx842_exec_icswx()530 * (De)compression provided by the NX842 coprocessor on IBM PowerNV systems.[all …]
11 bool "Cryptographic Coprocessor device"19 Provides the support for AMD Cryptographic Coprocessor (CCP) device35 Coprocessor. This module supports offload of SHA and AES algorithms.
17 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */18 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */31 /* Macro to save all non-coprocessor (extra) custom TIE and optional state58 /* Macro to save all non-coprocessor (extra) custom TIE and optional state91 /* Macro to save the state of TIE coprocessor AudioEngineLX.127 /* Macro to restore the state of TIE coprocessor AudioEngineLX.
18 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */19 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */32 /* Macro to save all non-coprocessor (extra) custom TIE and optional state73 /* Macro to save all non-coprocessor (extra) custom TIE and optional state