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/src/sys/dev/isci/scil/
H A Dscic_sds_controller_registers.h75 #define scic_sds_controller_smu_register_read(controller, reg) \ argument
77 (controller), \
78 (controller)->smu_registers->reg \
81 #define scic_sds_controller_smu_register_write(controller, reg, value) \ argument
83 (controller), \
84 (controller)->smu_registers->reg, \
93 #define scu_afe_register_write(controller, reg, value) \ argument
95 (controller), \
96 (controller)->scu_registers->afe.reg, \
100 #define scu_afe_register_read(controller, reg) \ argument
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H A Dscif_controller.h61 * by an SCIF user on a SCIF controller object.
73 * @brief This method will attempt to construct a framework controller object
77 * library object associated with the controller being constructed.
78 * @param[in] controller This parameter specifies the framework controller to
81 * controller object and will be used to associate with the
82 * framework controller.
84 * @return Indicate if the controller was successfully constructed or if
86 * @retval SCI_SUCCESS This value is returned if the controller was
89 * if the controller does not support the supplied oem parameter
92 * if the controller doesn't support the port configuration scheme
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H A Dscic_controller.h61 * by an SCIC user on a controller object.
125 SCI_CONTROLLER_HANDLE_T controller
132 * of other controller generated events. This method should be
141 SCI_CONTROLLER_HANDLE_T controller
158 * @brief This method will attempt to construct a controller object
162 * object associated with the controller being constructed.
163 * @param[in] controller This parameter specifies the controller to be
166 * controller object and will be used to associate with the core
167 * controller.
169 * @return Indicate if the controller was successfully constructed or if
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H A Dscif_sas_controller_state_handlers.c60 * of the controller states defined by the SCI_BASE_CONTROLLER state
84 * controller for execute the reset.
124 * controller object for which to validation the MDL.
156 * controller.
159 * controller object for whose remote devices are to be stopped.
204 * @brief This method continue to stop the controller after clear affiliation
208 * controller object to be stopped.
213 * of stopping controller.
233 // Attempt to stop the core controller. in scif_sas_controller_continue_to_stop()
241 "Controller:0x%x Status:0x%x unable to stop controller.\n", in scif_sas_controller_continue_to_stop()
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H A Dscic_sds_port_configuration_agent.c131 * @param[in] controller The controller object used for the port search.
142 SCIC_SDS_CONTROLLER_T * controller, in scic_sds_port_configuration_agent_find_port() argument
154 sci_base_object_get_logger(controller), in scic_sds_port_configuration_agent_find_port()
157 controller, phy in scic_sds_port_configuration_agent_find_port()
168 if (scic_controller_get_port_handle(controller, port_index, &port_handle) == SCI_SUCCESS) in scic_sds_port_configuration_agent_find_port()
196 * @param[in] controller This is the controller object that contains the
199 * the controller.
209 SCIC_SDS_CONTROLLER_T * controller, in scic_sds_port_configuration_agent_validate_ports() argument
218 sci_base_object_get_logger(controller), in scic_sds_port_configuration_agent_validate_ports()
221 controller, port_agent in scic_sds_port_configuration_agent_validate_ports()
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/src/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos9810-pinctrl.dtsi13 gpio-controller;
16 interrupt-controller;
21 gpio-controller;
24 interrupt-controller;
38 gpio-controller;
41 interrupt-controller;
55 gpio-controller;
58 interrupt-controller;
72 gpio-controller;
75 interrupt-controller;
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/src/sys/contrib/device-tree/Bindings/cache/
H A Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
17 "fsl,mpc8544-l2-cache-controller"
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/src/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dl2cache.txt1 Freescale L2 Cache Controller
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
17 "fsl,mpc8544-l2-cache-controller"
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/src/sys/dev/isci/
H A Disci_controller.c62 * @brief This user callback will inform the user that the controller has
65 * complete. Subsequently, the user should reset the controller.
67 * @param[in] controller This parameter specifies the controller that had
72 void scif_cb_controller_error(SCI_CONTROLLER_HANDLE_T controller, in scif_cb_controller_error() argument
81 * @brief This user callback will inform the user that the controller has
84 * @param[in] controller This parameter specifies the controller that was
92 void scif_cb_controller_start_complete(SCI_CONTROLLER_HANDLE_T controller, in scif_cb_controller_start_complete() argument
97 sci_object_get_association(controller); in scif_cb_controller_start_complete()
104 * the controller with CAM. in scif_cb_controller_start_complete()
128 * @brief This user callback will inform the user that the controller has
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H A Disci.c92 { 0x1d608086, "Intel(R) C600 Series Chipset SAS Controller" },
93 { 0x1d618086, "Intel(R) C600 Series Chipset SAS Controller (SATA mode)" },
94 { 0x1d628086, "Intel(R) C600 Series Chipset SAS Controller" },
95 { 0x1d638086, "Intel(R) C600 Series Chipset SAS Controller" },
96 { 0x1d648086, "Intel(R) C600 Series Chipset SAS Controller" },
97 { 0x1d658086, "Intel(R) C600 Series Chipset SAS Controller" },
98 { 0x1d668086, "Intel(R) C600 Series Chipset SAS Controller" },
99 { 0x1d678086, "Intel(R) C600 Series Chipset SAS Controller" },
100 { 0x1d688086, "Intel(R) C600 Series Chipset SAS Controller" },
101 { 0x1d698086, "Intel(R) C600 Series Chipset SAS Controller" },
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/src/sys/dev/ichiic/
H A Dig4_pci.c214 { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL},
215 { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL},
222 { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE},
223 { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE},
224 { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE},
225 { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE},
226 { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE},
227 { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
228 { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
229 { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
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/src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dsamsung-pinctrl.txt1 Samsung GPIO and Pin Mux/Config controller
4 controller. It controls the input/output settings on the available pads/pins
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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/src/sys/contrib/device-tree/Bindings/memory-controllers/fsl/
H A Dfsl,ddr.yaml7 title: Freescale DDR memory controller
15 pattern: "^memory-controller@[0-9a-f]+$"
21 - fsl,qoriq-memory-controller-v4.4
22 - fsl,qoriq-memory-controller-v4.5
23 - fsl,qoriq-memory-controller-v4.7
24 - fsl,qoriq-memory-controller-v5.0
25 - const: fsl,qoriq-memory-controller
27 - fsl,bsc9132-memory-controller
28 - fsl,mpc8536-memory-controller
29 - fsl,mpc8540-memory-controller
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/src/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5410-pinctrl.dtsi13 gpio-controller;
16 interrupt-controller;
21 gpio-controller;
24 interrupt-controller;
29 gpio-controller;
32 interrupt-controller;
37 gpio-controller;
40 interrupt-controller;
45 gpio-controller;
48 interrupt-controller;
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/src/sys/contrib/device-tree/Bindings/clock/
H A Dexynos5433-clock.txt3 The Exynos5433 clock controller generates and supplies clock to various
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
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/src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,imx8qxp-dc-intc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
7 title: Freescale i.MX8qxp Display Controller interrupt controller
10 The Display Controller has a built-in interrupt controller with the following
20 allowing it to use a global interrupt controller instead.
38 interrupt-controller: true
50 (display controller, content stream 0)
53 (display controller, content stream 0)
56 (display controller, content stream 0)
59 (display controller, safety stream 0)
62 (display controller, safety stream 0)
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H A Dvia,vt8500-intc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml#
7 title: VIA and WonderMedia SoCs Interrupt Controller
10 This is the interrupt controller used in single-core ARM SoCs made by
19 - $ref: /schemas/interrupt-controller.yaml#
31 Interrupt number raised by the IRQ0 output of this controller
32 Only used if this controller is chained
34 Interrupt number raised by the IRQ1 output of this controller
35 Only used if this controller is chained
37 Interrupt number raised by the IRQ2 output of this controller
38 Only used if this controller is chained
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/src/sys/powerpc/mpc85xx/
H A Dmpc85xx_cache.c55 {"fsl,8540-l2-cache-controller", 1},
56 {"fsl,8541-l2-cache-controller", 1},
57 {"fsl,8544-l2-cache-controller", 1},
58 {"fsl,8548-l2-cache-controller", 1},
59 {"fsl,8555-l2-cache-controller", 1},
60 {"fsl,8568-l2-cache-controller", 1},
61 {"fsl,b4420-l2-cache-controller", 1},
62 {"fsl,b4860-l2-cache-controller", 1},
63 {"fsl,bsc9131-l2-cache-controller", 1},
64 {"fsl,bsc9132-l2-cache-controller", 1},
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/src/sys/dev/ichsmb/
H A Dichsmb_pci.c41 * Support for the SMBus controller logical device which is part of the
42 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips.
124 PCI_DESCR("Intel 82801AA (ICH) SMBus controller") },
126 PCI_DESCR("Intel 82801AB (ICH0) SMBus controller") },
128 PCI_DESCR("Intel 82801BA (ICH2) SMBus controller") },
130 PCI_DESCR("Intel 82801CA (ICH3) SMBus controller") },
132 PCI_DESCR("Intel 82801DC (ICH4) SMBus controller") },
134 PCI_DESCR("Intel 82801EB (ICH5) SMBus controller") },
136 PCI_DESCR("Intel 82801FB (ICH6) SMBus controller") },
138 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") },
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/src/share/misc/
H A Dpci_vendors33 7a00 7A1000 Chipset Hyper Transport Bridge Controller
34 7a02 2K1000 / 7A1000 Chipset Advanced Peripheral Bus Controller
35 7a03 2K1000/2000 / 7A1000 Chipset Gigabit Ethernet Controller
36 7a04 2K1000 / 7A1000 Chipset OTG USB Controller
38 7a06 2K1000 / 7A1000 Chipset Display Controller
39 7a07 2K1000/2000 / 7A1000/2000 Chipset HD Audio Controller
40 7a08 2K1000 / 7A1000 Chipset 3Gb/s SATA AHCI Controller
42 7a0b 7A1000 Chipset SPI Controller
43 7a0c 2K2000 / 7A1000/2000 Chipset LPC Controller
44 7a0e 2K2000 AES Controller
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/src/sys/dev/usb/controller/
H A Duhci_pci.c33 /* Universal Host Controller Interface
38 /* The low level controller code for UHCI has been split into
74 #include <dev/usb/controller/uhci.h>
75 #include <dev/usb/controller/uhcireg.h>
106 return ("Intel 631XESB/632XESB/3100 USB controller USB-1"); in uhci_pci_match()
109 return ("Intel 631XESB/632XESB/3100 USB controller USB-2"); in uhci_pci_match()
112 return ("Intel 631XESB/632XESB/3100 USB controller USB-3"); in uhci_pci_match()
115 return ("Intel 631XESB/632XESB/3100 USB controller USB-4"); in uhci_pci_match()
118 return ("Intel 82371SB (PIIX3) USB controller"); in uhci_pci_match()
121 return ("Intel 82371AB/EB (PIIX4) USB controller"); in uhci_pci_match()
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/src/sys/contrib/device-tree/Bindings/pci/
H A Dpci-msi.txt23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
53 the root complex and MSI controller do not pass sideband data with MSI
54 writes, this property may be used to describe the MSI controller(s)
66 msi: msi-controller@a {
68 compatible = "vendor,some-controller";
69 msi-controller;
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/src/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A Ddata-fabric.json4 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
12 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
20 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
28 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
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/src/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Ddata-fabric.json4 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
12 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
20 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
28 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
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/src/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Ddata-fabric.json4 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
12 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
20 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
28 …"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Contro…
36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
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