| /linux-3.3/arch/blackfin/mach-bf548/include/mach/ |
| D | defBF548.h | 16 /* CAN Controller 1 Config 1 Registers */
18 #define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Re…
19 #define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Regist…
20 #define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Reg…
21 #define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset R…
22 #define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Reg…
23 #define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Regist…
24 #define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending …
25 #define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Reg…
26 #define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interru…
[all …]
|
| D | defBF544.h | 73 /* CAN Controller 1 Config 1 Registers */
75 #define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Re…
76 #define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Regist…
77 #define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Reg…
78 #define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset R…
79 #define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Reg…
80 #define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Regist…
81 #define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending …
82 #define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Reg…
83 #define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interru…
[all …]
|
| D | defBF54x_base.h | 31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
202 #define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods …
203 #define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register …
692 #define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods …
693 #define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register …
1040 /* CAN Controller 0 Config 1 Registers */
1042 #define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Re…
1043 #define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Regist…
1044 #define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Reg…
1045 #define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset R…
[all …]
|
| /linux-3.3/drivers/block/ |
| D | DAC960.c | 177 static void DAC960_AnnounceDriver(DAC960_Controller_T *Controller) in DAC960_AnnounceDriver() argument
181 DAC960_DriverDate " *****\n", Controller); in DAC960_AnnounceDriver()
183 "<lnz@dandelion.com>\n", Controller); in DAC960_AnnounceDriver()
191 static bool DAC960_Failure(DAC960_Controller_T *Controller, in DAC960_Failure() argument
194 DAC960_Error("While configuring DAC960 PCI RAID Controller at\n", in DAC960_Failure()
195 Controller); in DAC960_Failure()
196 if (Controller->IO_Address == 0) in DAC960_Failure()
198 "PCI Address 0x%X\n", Controller, in DAC960_Failure()
199 Controller->Bus, Controller->Device, in DAC960_Failure()
200 Controller->Function, Controller->PCI_Address); in DAC960_Failure()
[all …]
|
| /linux-3.3/drivers/usb/musb/ |
| D | musbhsdma.c | 2 * MUSB OTG driver - support for Mentor's DMA controller
50 struct musb_dma_controller *controller = container_of(c, in dma_controller_stop() local
51 struct musb_dma_controller, controller); in dma_controller_stop()
52 struct musb *musb = controller->private_data; in dma_controller_stop()
56 if (controller->used_channels != 0) { in dma_controller_stop()
57 dev_err(musb->controller, in dma_controller_stop()
58 "Stopping DMA controller while channel active\n"); in dma_controller_stop()
61 if (controller->used_channels & (1 << bit)) { in dma_controller_stop()
62 channel = &controller->channel[bit].channel; in dma_controller_stop()
65 if (!controller->used_channels) in dma_controller_stop()
[all …]
|
| D | ux500_dma.c | 38 struct ux500_dma_controller *controller; member
49 struct dma_controller controller; member
67 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", in ux500_dma_callback()
92 ux500_channel->controller->phy_base); in ux500_configure_channel()
93 struct musb *musb = ux500_channel->controller->private_data; in ux500_configure_channel()
95 dev_dbg(musb->controller, in ux500_configure_channel()
140 struct ux500_dma_controller *controller = container_of(c, in ux500_dma_channel_allocate() local
141 struct ux500_dma_controller, controller); in ux500_dma_channel_allocate()
143 struct musb *musb = controller->private_data; in ux500_dma_channel_allocate()
154 max_ch = is_tx ? controller->num_tx_channels : in ux500_dma_channel_allocate()
[all …]
|
| D | cppi_dma.c | 77 * Start DMA controller
79 * Initialize the DMA controller as necessary.
116 c->controller = cppi; in cppi_pool_init()
135 struct cppi *cppi = c->controller; in cppi_pool_free()
140 c->controller = NULL; in cppi_pool_free()
154 struct cppi *controller; in cppi_controller_start() local
158 controller = container_of(c, struct cppi, controller); in cppi_controller_start()
160 /* do whatever is necessary to start controller */ in cppi_controller_start()
161 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { in cppi_controller_start()
162 controller->tx[i].transmit = true; in cppi_controller_start()
[all …]
|
| /linux-3.3/drivers/spi/ |
| D | Kconfig | 15 controller and a chipselect. Most SPI slaves don't support
19 eeprom and flash memory, codecs and various other controller
36 sysfs, and debugfs support in SPI controller and protocol drivers.
47 If your system has an master-capable SPI controller (which
49 controller and the protocol drivers for the SPI slave chips
54 comment "SPI Master Controller Drivers"
57 tristate "Altera SPI Controller"
60 This is the driver for the Altera SPI Controller.
63 tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
67 This enables support for the SPI controller present on the
[all …]
|
| /linux-3.3/drivers/usb/host/ |
| D | Kconfig | 2 # USB Host Controller Drivers
4 comment "USB Host Controller Drivers"
14 Enable this option to support this chip in host controller mode.
24 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
25 "SuperSpeed" host controller hardware.
31 bool "Debugging for the xHCI host controller"
34 Say 'Y' to turn on debugging for the xHCI host controller driver.
44 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
45 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
46 If your USB host controller supports USB 2.0, you will likely want to
[all …]
|
| /linux-3.3/drivers/eisa/ |
| D | eisa.ids | 22 ACE4010 "ACME Tape Controller"
24 ACE6010 "ACME Disk Controller"
87 ALR8580 "Advanced Disk Array Caching EISA Controller"
96 AMI15E1 "AMI Normal Single Ended EISA SCSI CACHING Controller-Ver 1.22"
101 AMI44D2 "AMI Fast Single Ended EISA SCSI CACHING Controller"
130 AVM0001 "AVM ISDN-Controller A1"
136 BUS6001 "BusTek/BusLogic Bt760 32-Bit Bus Master EISA-to-Ethernet Controller"
137 BUS6301 "BusTek/BusLogic Bt763E EISA 32-Bit 82596-based Ethernet Controller"
138 CCI0000 "Cache Computers, Inc. Memory Refresh Controller"
149 CHAA041 "Chase AT4 Intelligent Serial Controller"
[all …]
|
| /linux-3.3/drivers/mmc/host/ |
| D | Kconfig | 2 # MMC/SD host controller drivers
5 comment "MMC/SD/SDIO Host Controller Drivers"
28 tristate "Secure Digital Host Controller Interface support"
31 This selects the generic Secure Digital Host Controller Interface.
35 If you have a controller with this interface, say Y or M here. You
52 and performing I/O to a SDHCI controller through a bus that
64 This selects the PCI Secure Digital Host Controller Interface.
67 If you have a controller with this interface, say Y or M here.
72 bool "Ricoh MMC Controller Disabler (EXPERIMENTAL)"
75 This adds a pci quirk to disable Ricoh MMC Controller. This
[all …]
|
| /linux-3.3/include/linux/mmc/ |
| D | sdhci.h | 2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
26 /* Controller doesn't honor resets unless we touch the clock register */
28 /* Controller has bad caps bits, but really supports DMA */
30 /* Controller doesn't like to be reset when there is no card inserted. */
32 /* Controller doesn't like clearing the power reg before a change */
34 /* Controller has flaky internal state so reset it on each ios change */
36 /* Controller has an unusable DMA engine */
38 /* Controller has an unusable ADMA engine */
40 /* Controller can only DMA from 32-bit aligned addresses */
42 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
[all …]
|
| /linux-3.3/arch/arm/boot/dts/ |
| D | exynos4210.dtsi | 28 gic:interrupt-controller@10490000 {
31 interrupt-controller;
173 gpio-controller;
176 gpa0: gpio-controller@11400000 {
182 gpa1: gpio-controller@11400020 {
188 gpb: gpio-controller@11400040 {
194 gpc0: gpio-controller@11400060 {
200 gpc1: gpio-controller@11400080 {
206 gpd0: gpio-controller@114000A0 {
212 gpd1: gpio-controller@114000C0 {
[all …]
|
| /linux-3.3/arch/arm/mach-at91/include/mach/ |
| D | at91rm9200.h | 22 #define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
23 #define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
24 #define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
25 #define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
34 #define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35 #define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36 #define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
45 #define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
46 #define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
47 #define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
[all …]
|
| D | at91sam9g45.h | 21 #define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
22 #define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
23 #define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
24 #define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
35 #define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
36 #define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
38 #define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
39 #define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
40 #define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
42 #define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
[all …]
|
| /linux-3.3/Documentation/devicetree/bindings/ |
| D | marvell.txt | 1 Marvell Discovery mv64[345]6x System Controller chips
4 The Marvell mv64[345]60 series of system controller chips contain
7 the system controller chip itself and each of the peripherals
11 1) The /system-controller node
13 This node is used to represent the system-controller and must be
14 present when the system uses a system controller chip. The top-level
15 system-controller node contains information that is global to all
16 devices within the system controller chip. The node name begins
17 with "system-controller" followed by the unit address, which is
19 controller chip.
[all …]
|
| /linux-3.3/arch/ia64/sn/kernel/ |
| D | io_init.c | 121 * sn_pci_legacy_window_fixup - Create PCI controller windows for
128 sn_legacy_pci_window_fixup(struct pci_controller *controller, in sn_legacy_pci_window_fixup() argument
131 controller->window = kcalloc(2, sizeof(struct pci_window), in sn_legacy_pci_window_fixup()
133 BUG_ON(controller->window == NULL); in sn_legacy_pci_window_fixup()
134 controller->window[0].offset = legacy_io; in sn_legacy_pci_window_fixup()
135 controller->window[0].resource.name = "legacy_io"; in sn_legacy_pci_window_fixup()
136 controller->window[0].resource.flags = IORESOURCE_IO; in sn_legacy_pci_window_fixup()
137 controller->window[0].resource.start = legacy_io; in sn_legacy_pci_window_fixup()
138 controller->window[0].resource.end = in sn_legacy_pci_window_fixup()
139 controller->window[0].resource.start + 0xffff; in sn_legacy_pci_window_fixup()
[all …]
|
| /linux-3.3/drivers/char/agp/ |
| D | frontend.c | 290 * These routines manage the current controller, and the list of
296 struct agp_controller *controller; in agp_find_controller_by_pid() local
298 controller = agp_fe.controllers; in agp_find_controller_by_pid()
300 while (controller != NULL) { in agp_find_controller_by_pid()
301 if (controller->pid == id) in agp_find_controller_by_pid()
302 return controller; in agp_find_controller_by_pid()
303 controller = controller->next; in agp_find_controller_by_pid()
311 struct agp_controller *controller; in agp_create_controller() local
313 controller = kzalloc(sizeof(struct agp_controller), GFP_KERNEL); in agp_create_controller()
314 if (controller == NULL) in agp_create_controller()
[all …]
|
| /linux-3.3/arch/powerpc/boot/dts/ |
| D | mucmc52.dts | 22 gpio-controller;
27 gpio-controller;
32 gpio-controller;
37 gpio-controller;
188 simple100: gpio-controller-100@3,600100 {
191 gpio-controller;
194 simple104: gpio-controller-104@3,600104 {
197 gpio-controller;
200 simple200: gpio-controller-200@3,600200 {
203 gpio-controller;
[all …]
|
| /linux-3.3/Documentation/devicetree/bindings/gpio/ |
| D | gpio.txt | 12 gpio-phandle : phandle to gpio controller node
14 (controller specific)
25 gpio-controller
29 gpio-controller
38 Note that gpio-specifier length is controller dependent. In the
44 Exact meaning of each specifier cell is controller specific, and must
54 and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
56 2) gpio-controller nodes
59 Every GPIO controller node must both an empty "gpio-controller"
62 Example of two SOC GPIO banks defined as gpio-controller nodes:
[all …]
|
| /linux-3.3/drivers/pci/hotplug/ |
| D | cpqphp.h | 2 * Compaq Hot Plug Controller Driver
152 /* offsets to the controller registers based on the above structure layout */
275 struct controller *ctrl;
291 struct controller { struct
292 struct controller *next; argument
295 void __iomem *hpc_reg; /* cookie for our pci controller location */ argument
307 u8 bus; /* bus number for the pci hotplug controller */ argument
396 #define msg_HPC_rev_error "Unsupported revision of the PCI hot plug controller found.\n"
397 #define msg_HPC_non_compaq_or_intel "The PCI hot plug controller is not supported by this driver.\n"
406 /* debugfs functions for the hotplug controller info */
[all …]
|
| /linux-3.3/Documentation/devicetree/bindings/c6x/ |
| D | interrupt.txt | 4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
31 * C64x+ Megamodule Interrupt Controller
35 may be cascaded into the core interrupt controller. The megamodule PIC
36 has a total of 12 outputs cascading into the core interrupt controller.
39 the core interrupt controller. When an individual interrupt is cascaded,
41 considered to have the core interrupt controller as the parent.
46 - interrupt-controller
[all …]
|
| /linux-3.3/drivers/edac/ |
| D | ppc4xx_edac.c | 29 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
32 * As realized in the 405EX[r], this controller features:
47 * As realized in the 440SP and 440SPe, this controller changes/adds:
60 * As realized in the 460EX and 460GT, this controller changes/adds:
74 * At present, this driver has ONLY been tested against the controller
81 * other realizations of this controller listed above.
84 * realizations of this controller as well as broken apart to handle
92 * For this controller, unfortunately, correctable errors report
163 * PPC4xx SDRAM memory controller private instance data
215 * set based on the aforementioned variant controller realizations.
[all …]
|
| /linux-3.3/Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 44 1.b.i) The "Flipper" interrupt controller node
46 Represents the "Flipper" interrupt controller within the "Hollywood" chip.
47 The node for the "Flipper" interrupt controller must be placed under
54 - interrupt-controller
100 1.g) The Open Host Controller Interface (OHCI) nodes
102 Represent the USB 1.x Open Host Controller Interfaces.
110 1.h) The Enhanced Host Controller Interface (EHCI) node
112 Represents the USB 2.0 Enhanced Host Controller Interface.
120 1.i) The Secure Digital Host Controller Interface (SDHCI) nodes
122 Represent the Secure Digital Host Controller Interfaces.
[all …]
|
| /linux-3.3/drivers/usb/gadget/ |
| D | Kconfig | 3 # (a) a peripheral controller, and
13 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
26 you need a low level bus controller driver, and some software
35 peripheral/device side bus controller, and a "gadget driver" for
51 Many controller and gadget drivers will print some debugging
67 (for a peripheral controller). The information in these
117 # USB Peripheral Controller Support
127 prompt "USB Peripheral Controller"
129 A USB device uses a controller to talk to its host.
131 Many controller drivers are platform-specific; these
[all …]
|