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/qemu/linux-headers/linux/
H A Dvfio_ccw.h28 * Note: this is controlled by a capability
40 * Note: this is controlled by a capability
49 * Note: this is controlled by a capability
/qemu/hw/sensor/
H A Dmax34451.c70 | 0 | Power supply monitored by RS0, controlled by PSEN0, and |
73 | 1 | Power supply monitored by RS1, controlled by PSEN1, and |
76 | 2 | Power supply monitored by RS2, controlled by PSEN2, and |
79 | 3 | Power supply monitored by RS3, controlled by PSEN3, and |
82 | 4 | Power supply monitored by RS4, controlled by PSEN4, and |
85 | 5 | Power supply monitored by RS5, controlled by PSEN5, and |
88 | 6 | Power supply monitored by RS6, controlled by PSEN6, and |
91 | 7 | Power supply monitored by RS7, controlled by PSEN7, and |
94 | 8 | Power supply monitored by RS8, controlled by PSEN8, and |
97 | 9 | Power supply monitored by RS9, controlled by PSEN9, and |
[all …]
/qemu/hw/misc/
H A Dlasi.c107 /* Controlled by lasi_chip_mem_valid above. */ in lasi_chip_read_with_attrs()
187 /* Controlled by lasi_chip_mem_valid above. */ in lasi_chip_write_with_attrs()
H A Domap_clk.c254 /* No-idle controlled by "tc_ck" */
261 /* No-idle controlled by "tc_ck" */
280 /* No-idle controlled by "tc_ck" */
/qemu/include/standard-headers/linux/
H A Dvirtio_i2c.h25 * @addr: the controlled device address
/qemu/target/arm/
H A Ddebug_helper.c111 * are always enabled. Otherwise they are controlled by in aa32_generate_debug_exceptions()
124 * is enabled. On real hardware this is controlled by external in aa32_generate_debug_exceptions()
787 * Check for traps to "powerdown debug" registers, which are controlled
808 * Check for traps to "debug ROM" registers, which are controlled
829 * Check for traps to general debug registers, which are controlled
861 * is implemented then these are controlled by MDCR_EL2.TDCC for
862 * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
864 * For EL0, they are also controlled by MDSCR_EL1.TDCC.
/qemu/docs/devel/testing/
H A Dci-jobs.rst.inc88 Maintainer controlled job variables
134 Contributor controlled runtime variables
/qemu/include/hw/pci/
H A Dshpc.h32 /* Bus controlled by this SHPC */
/qemu/include/hw/virtio/
H A Dvirtio-scsi.h18 /* Override CDB/sense data size: they are dynamic (guest controlled) in QEMU */
/qemu/docs/specs/
H A Dvmw_pvscsi-spec.rst65 Interrupts are controlled via the ``PVSCSI_REG_OFFSET_INTR_MASK``
/qemu/include/hw/ppc/
H A Dxive.h106 * an Event State Buffer (ESB) array and can be controlled by MMIOs.
173 * controlled.
245 * controlled by MMIO. P indicates that an interrupt is pending (has
/qemu/hw/ssi/
H A Dmss-spi.c221 * Chip Select(CS) is automatically controlled by this controller. in spi_flush_txfifo()
226 * has to be controlled automatically by controller. Bits SS[7:1] are for in spi_flush_txfifo()
/qemu/docs/tools/
H A Dqemu-storage-daemon.rst16 ``qemu-img``, and ``qemu-nbd`` in a long-running process controlled via QMP
19 perform other disk-related operations. The daemon is controlled via a QMP
/qemu/docs/system/i386/
H A Dhyperv.rst90 is needed to enable Hyper-V synthetic timers. SynIC is controlled through MSRs
98 CPU controlled through HV_X64_MSR_STIMER0_CONFIG..HV_X64_MSR_STIMER3_COUNT
H A Dsgx.rst88 controlled via -cpu are prefixed with "sgx", e.g.::
/qemu/hw/pci-host/
H A Ddino.c177 /* Controlled by dino_chip_mem_valid above. */ in dino_chip_read_with_attrs()
265 /* Controlled by dino_chip_mem_valid above. */ in dino_chip_write_with_attrs()
/qemu/hw/display/
H A Dpl110.c236 * 565 format. The mux is typically controlled by in pl110_update_display()
238 * This is controlled by a GPIO input pin in pl110_update_display()
/qemu/rust/qemu-api/src/
H A Derror.rs270 // SAFETY: all arguments are controlled by this function in clone_to_foreign()
326 // SAFETY: all arguments are controlled by this function in error_for_test()
/qemu/
H A D.travis.yml59 # Main build & test - rarely overridden - controlled by TEST_CMD
/qemu/hw/m68k/
H A Dq800-glue.c42 * controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
/qemu/docs/system/
H A Dintroduction.rst147 - How the system is displayed, how it is managed and controlled or
/qemu/docs/config/
H A Dq35-virtio-graphical.cfg197 # a USB tablet so that graphical guests can be controlled
H A Dmach-virt-graphical.cfg247 # guests can be controlled appropriately.
/qemu/tests/qtest/
H A Dsse-timer-test.c111 * is on port 0 of PPC0, controlled by bit 0 of this register. in test_timer()
/qemu/docs/
H A Dimage-fuzzer.txt217 The fuzzer can be controlled via template, seed and action vector;

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