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/linux-6.8/Documentation/devicetree/bindings/interrupt-controller/
Dsamsung,exynos4210-combiner.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
23 A single node in the device tree is used to describe the interrupt combiner
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/linux-6.8/drivers/irqchip/
Dexynos-combiner.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * Combiner irqchip for EXYNOS
48 return combiner_data->base; in combiner_base()
53 u32 mask = 1 << (data->hwirq % 32); in combiner_mask_irq()
60 u32 mask = 1 << (data->hwirq % 32); in combiner_unmask_irq()
76 status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS); in combiner_handle_cascade_irq()
78 status &= chip_data->irq_mask; in combiner_handle_cascade_irq()
83 combiner_irq = chip_data->hwirq_offset + __ffs(status); in combiner_handle_cascade_irq()
97 struct irq_chip *chip = irq_get_chip(chip_data->parent_irq); in combiner_set_affinity()
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/linux-6.8/arch/arm/boot/dts/samsung/
Dexynos5.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
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Dexynos4212.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
39 compatible = "arm,cortex-a9";
42 clock-names = "cpu";
43 operating-points-v2 = <&cpu0_opp_table>;
44 #cooling-cells = <2>; /* min followed by max */
49 compatible = "arm,cortex-a9";
52 clock-names = "cpu";
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Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
23 #address-cells = <1>;
24 #size-cells = <0>;
26 cpu-map {
45 compatible = "arm,cortex-a9";
48 clock-names = "cpu";
49 operating-points-v2 = <&cpu0_opp_table>;
50 #cooling-cells = <2>; /* min followed by max */
55 compatible = "arm,cortex-a9";
58 clock-names = "cpu";
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Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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