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/qemu/scripts/simplebench/
H A Dtable_templater.py47 def gen(self, column, row): argument
56 result.append(column[i])
H A Dresults_to_text.py84 # Add row of difference between columns. For each column starting from
86 row = ['', ''] # case name and first column
H A Dbench-example.py61 # the column, other fields are handled by bench_func.
H A Dimg_bench_templater.py61 column templating: {var1|var2|...} - test will use different values in
H A Dbench_write_req.py154 # for the column, other fields are handled by bench_func.
/qemu/docs/specs/
H A Dppc-spapr-xive.rst260 - The ``LISN`` column outputs the interrupt number of the source in
262 - The ``PQ`` column reflects the state of the PQ bits of the source :
273 - The ``EISN`` column is the event data that will be queued in the event
275 - The ``CPU/PRIO`` column is the tuple defining the CPU number and
277 - The ``EQ`` column outputs :
/qemu/tests/tcg/multiarch/
H A Dtest-aes-main.c.inc23 * column-major, whereas C is row-major. Therefore to get the bytes
27 * so the "After SubBytes" column is omitted, using only the combined
28 * result "After ShiftRows" column.
/qemu/docs/sphinx-static/
H A Dtheme_overrides.css141 /* content column
216 two-column nature */
221 /* but the content column itself should still be less than ~80ch. */
/qemu/scripts/ci/
H A Dcoverage-summary.sh24 column -t rejoined.txt > final.txt
/qemu/scripts/
H A Dcompare-machine-types.py257 column = []
261 column.append(mt.compat_props[driver][prop])
264 column.append(self._qemu_drivers.get_prop(driver, prop))
265 table.append(pd.DataFrame({name: column}))
/qemu/tests/lcitool/projects/
H A Dqemu.yml15 - column
/qemu/scripts/coccinelle/
H A Derr-bad-newline.cocci49 print("%s:%s:%s:%s" % (p[0].file, p[0].line, p[0].column, fmt))
/qemu/hw/mem/
H A Dcxl_type3_stubs.c35 bool has_column, uint16_t column, in qmp_cxl_inject_dram_event() argument
/qemu/scripts/codeconverter/codeconverter/
H A Dutils.py51 """Return line and column for a char position in string
/qemu/hw/display/
H A Dssd0303.c106 case 0x00 ... 0x0f: /* Set lower column address. */ in ssd0303_send()
109 case 0x10 ... 0x20: /* Set higher column address. */ in ssd0303_send()
H A Dssd0323.c113 case 0x15: /* Set column. */ in OBJECT_DECLARE_SIMPLE_TYPE()
247 /* TODO: Implement row/column remapping. */ in ssd0323_update_display()
H A Dvmware_vga.c465 int column; in vmsvga_fill_rect() local
485 for (column = width; column > 0; column--) { in vmsvga_fill_rect()
H A Dartist.c388 int line, endline, lineincr, startcolumn, endcolumn, columnincr, column; in block_move() local
436 for (column = startcolumn; column != endcolumn; column += columnincr) { in block_move()
/qemu/hw/nvram/
H A Dxlnx-versal-efuse-ctrl.c59 FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
285 bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL); in efuse_anchor_bits_check()
290 bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL); in efuse_anchor_bits_check()
450 FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN)); in efuse_pgm_addr_postw()
H A Dxlnx-zynqmp-efuse.c58 FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
196 #define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN) argument
/qemu/qapi/
H A Dcxl.json127 # @column: Column address within the DRAM.
140 '*column': 'uint16', '*correction-mask': [ 'uint64' ]
/qemu/include/hw/cxl/
H A Dcxl_events.h145 uint16_t column; member
/qemu/python/qemu/utils/
H A D__init__.py69 characters that display using a single monospace column.
/qemu/include/standard-headers/drm/
H A Ddrm_fourcc.h525 * chunks column-major, with a platform-dependent height. On top of that the
543 * are arranged in four groups (two wide, two high) with column-major layout.
545 * out as 2x2 column-major.
1060 * The pitch between the start of each column is set to optimally
1062 * of column width in the modifier (we can't use the stride value due
1066 * Note that the column height for this format modifier is the same
1067 * for all of the planes, assuming that each column contains both Y
1069 * image from Y to reduce the column height, which is not supported
1104 * moving from one column to the next doesn't hit the same SDRAM page
/qemu/hw/sh4/
H A Dsh7750_regs.h873 #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */
874 #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */
875 #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */
876 #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */
877 #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */

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