| /linux-5.10/Documentation/devicetree/bindings/arm/marvell/ |
| D | coherency-fabric.txt | 1 Coherency fabric
9 * "marvell,coherency-fabric", to be used for the coherency fabric of
12 * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
15 * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
18 - reg: Should contain coherency fabric registers location and
21 * For "marvell,coherency-fabric", the first pair for the coherency
24 * For "marvell,armada-375-coherency-fabric", only one pair is needed
27 * For "marvell,armada-380-coherency-fabric", only one pair is needed
37 coherency-fabric@d0020200 {
38 compatible = "marvell,coherency-fabric";
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| /linux-5.10/arch/arm/mach-mvebu/ |
| D | coherency.c | 2 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
15 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
16 * responsible for ensuring hardware coherency between all CPUs and between
17 * CPUs and I/O masters. This file initializes the coherency fabric and
18 * supplies basic routines for configuring and controlling hardware coherency
21 #define pr_fmt(fmt) "mvebu-coherency: " fmt
37 #include "coherency.h"
45 /* Coherency fabric registers */
56 {.compatible = "marvell,coherency-fabric",
58 {.compatible = "marvell,armada-375-coherency-fabric",
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| D | coherency_ll.S | 2 * Coherency fabric: low level functions
13 * coherency fabric. This function is called by each of the secondary
28 * Returns the coherency base address in r1 (r0 is untouched), or 0 if
29 * the coherency fabric is not enabled.
37 * MMU is disabled, use the physical address of the coherency
38 * base address, (or 0x0 if the coherency fabric is not mapped)
46 * MMU is enabled, use the virtual address of the coherency
56 * Returns the coherency CPU mask in r3 (r0 is untouched). This
57 * coherency CPU mask can be used with the coherency fabric
60 * have to care about endianness issues while accessing the coherency
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| D | coherency.h | 2 * arch/arm/mach-mvebu/include/mach/coherency.h
5 * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
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| D | headsmp.S | 16 * the coherency fabric by writing to 2 registers. Currently the base
28 * We add the CPU to the coherency fabric and then jump to secondary
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| /linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | ccf.txt | 1 Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
5 The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
11 fsl,corenet1-cf - CoreNet coherency fabric version 1.
14 fsl,corenet2-cf - CoreNet coherency fabric version 2.
31 Specifies the number of Coherency Subdomain ID Port Mapping
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| D | cpus.txt | 27 Definition: The Coherency Subdomain ID Port Mapping Registers and
29 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
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| D | pamu.txt | 36 The Coherency Subdomain ID Port Mapping Registers and
38 CoreNet Coherency fabric (CCF), provide a CoreNet
39 Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
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| D | mcm.txt | 2 MPX LAW & Coherency Module Device Tree Binding
35 MPX Coherency Module Node
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| D | ecm.txt | 2 E500 LAW & Coherency Module Device Tree Binding
35 E500 Coherency Module Node
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| /linux-5.10/Documentation/arm/ |
| D | cluster-pm-race-avoidance.rst | 6 cluster setup and teardown operations and to manage hardware coherency
33 mechanisms like Linux spinlocks may rely on coherency mechanisms which
73 enabling coherency.
83 coherency exit.
160 A CPU cannot start participating in hardware coherency until the
178 start participating in local coherency.
201 While in this state, the CPU exits coherency, including any
318 enabling of hardware coherency at the cluster level and any
323 setup to enable other CPUs in the cluster to enter coherency
329 cluster-level setup and hardware coherency complete
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| /linux-5.10/arch/mips/mti-malta/ |
| D | malta-setup.c | 101 pr_info("Enabled Bonito CPU coherency\n"); in plat_enable_iocoherency()
109 pr_info("Disabled Bonito IOBC coherency\n"); in plat_enable_iocoherency()
115 pr_info("Enabled Bonito IOBC coherency\n"); in plat_enable_iocoherency()
118 /* Nothing special needs to be done to enable coherency */ in plat_enable_iocoherency()
122 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); in plat_enable_iocoherency()
135 pr_info("Hardware DMA cache coherency disabled\n"); in plat_setup_iocoherency()
137 pr_info("Hardware DMA cache coherency enabled\n"); in plat_setup_iocoherency()
140 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); in plat_setup_iocoherency()
142 pr_info("Software DMA cache coherency enabled\n"); in plat_setup_iocoherency()
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| /linux-5.10/Documentation/vm/ |
| D | cleancache.rst | 75 other sharers. The kernel is responsible for ensuring coherency between
79 Note that cleancache must enforce put-put-get coherency and get-get
80 coherency. For the former, if two puts are made to the same handle but
82 subsequent get can never return the stale data (AAA). For get-get coherency,
164 coherency (via cleancache_invalidate operations) between cleancache,
199 a great deal of race conditions and potential coherency issues
241 - To ensure coherency/correctness, the FS must ensure that all
244 - To ensure coherency/correctness, either inode numbers must
266 there would be potential coherency issues if/when the inode
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| /linux-5.10/drivers/memory/ |
| D | fsl-corenet-cf.c | 3 * CoreNet Coherency Fabric error reporting
76 #define ERRDET_CV (1 << 1) /* Coherency Violation */
154 dev_crit(ccf->dev, "Coherency Violation\n"); in ccf_irq()
277 MODULE_DESCRIPTION("Freescale CoreNet Coherency Fabric error reporting");
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| D | Kconfig | 75 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
156 Coherency Fabric. Errors reported include accesses to
159 represents a coherency violation.
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| /linux-5.10/Documentation/filesystems/ |
| D | ocfs2.rst | 106 coherency=full (*) Disallow concurrent O_DIRECT writes, cluster inode
108 therefore full cluster coherency is guaranteed even
110 coherency=buffered Allow concurrent O_DIRECT writes without EX lock among
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| /linux-5.10/arch/arm/mach-shmobile/ |
| D | platsmp-scu.c | 35 /* enable SCU and cache coherency on booting CPU */ in shmobile_smp_scu_prepare_cpus()
56 /* disable cache coherency */ in shmobile_smp_scu_cpu_die()
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| /linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | uncore.json | 247 "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
248 "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
259 "BriefDescription": "Number of requests allocated in Coherency Tracker.",
260 "PublicDescription": "Number of requests allocated in Coherency Tracker.",
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| /linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | uncore.json | 247 "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
248 "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
259 "BriefDescription": "Number of requests allocated in Coherency Tracker.",
260 "PublicDescription": "Number of requests allocated in Coherency Tracker.",
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| /linux-5.10/arch/arm/mach-spear/ |
| D | hotplug.c | 26 * Turn off coherency in cpu_enter_lowpower()
94 * coherency, and then restore interrupts in spear13xx_cpu_die()
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| /linux-5.10/tools/perf/pmu-events/arch/arm64/ |
| D | armv8-recommended.json | 45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
111 "PublicDescription": "Level 2 data cache Write-Back, cleaning and coherency",
114 "BriefDescription": "L2D cache Write-Back, cleaning and coherency"
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| /linux-5.10/arch/arm/mm/ |
| D | cache-v4.S | 68 * Ensure coherency between the Icache and the Dcache in the
81 * Ensure coherency between the Icache and the Dcache in the
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| /linux-5.10/arch/arm/include/asm/ |
| D | cacheflush.h | 71 * Ensure coherency between the Icache and the Dcache in the
79 * Ensure coherency between the Icache and the Dcache in the
91 * DMA Cache Coherency
433 * - Clear the ACTLR "SMP" bit to disable local coherency
465 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
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| /linux-5.10/arch/arm/mach-exynos/ |
| D | mcpm-exynos.c | 45 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
159 * Disable cluster-level coherency by masking in exynos_cluster_cache_disable()
204 * Enable cluster-level coherency, in preparation for turning on the MMU.
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| /linux-5.10/Documentation/filesystems/caching/ |
| D | backend-api.rst | 300 * Check coherency state of an object [mandatory]::
590 * Perform coherency check on an object::
596 This asks the netfs to perform a coherency check on an object that has
604 The coherency data indicates the object is valid as is.
607 The coherency data needs updating, but otherwise the object is
611 The coherency data indicates that the object is obsolete and should
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