Searched full:cmn_pll (Results 1 – 5 of 5) sorted by relevance
| /linux-6.15/drivers/clk/qcom/ |
| D | ipq-cmn-pll.c | 161 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); in clk_cmn_pll_recalc_rate() local
168 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); in clk_cmn_pll_recalc_rate()
192 struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); in clk_cmn_pll_set_rate() local
204 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, in clk_cmn_pll_set_rate()
215 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, in clk_cmn_pll_set_rate()
221 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, in clk_cmn_pll_set_rate()
229 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, in clk_cmn_pll_set_rate()
238 ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, in clk_cmn_pll_set_rate()
244 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, in clk_cmn_pll_set_rate()
250 return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, in clk_cmn_pll_set_rate()
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| /linux-6.15/Documentation/devicetree/bindings/clock/ |
| D | qcom,ipq9574-nsscc.yaml | 28 - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
29 - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
74 <&cmn_pll NSS_1200MHZ_CLK>,
75 <&cmn_pll PPE_353MHZ_CLK>,
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| D | qcom,ipq9574-cmn-pll.yaml | 66 cmn_pll: clock-controller@9b000 {
74 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
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| /linux-6.15/drivers/net/mdio/ |
| D | mdio-ipq4019.c | 256 /* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 in ipq_mdio_reset()
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| /linux-6.15/arch/arm64/boot/dts/qcom/ |
| D | ipq9574.dtsi | 351 cmn_pll: clock-controller@9b000 { label
359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
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