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/linux-6.8/sound/soc/intel/common/
Dsoc-acpi-intel-cml-match.c3 * soc-acpi-intel-cml-match.c - tables and support for CML ACPI enumeration.
48 .sof_tplg_filename = "sof-cml-rt1011-rt5682.tplg",
55 .sof_tplg_filename = "sof-cml-rt1011-rt5682.tplg",
62 .sof_tplg_filename = "sof-cml-rt5682-max98357a.tplg",
67 .sof_tplg_filename = "sof-cml-rt5682.tplg",
74 .sof_tplg_filename = "sof-cml-da7219-max98357a.tplg",
81 .sof_tplg_filename = "sof-cml-da7219-max98390.tplg",
86 .sof_tplg_filename = "sof-cml-es8336", /* the tplg suffix is added at run time */
287 .sof_tplg_filename = "sof-cml-rt711-rt1308-rt715.tplg",
293 .sof_tplg_filename = "sof-cml-rt711-rt1316-rt714.tplg",
[all …]
Dsoc-acpi-intel-cnl-match.c34 /* cnl and cml are identical */
35 .sof_tplg_filename = "sof-cml-es8336", /* the tplg suffix is added at run time */
80 .sof_tplg_filename = "sof-cml-rt711-rt1308-rt715.tplg",
86 .sof_tplg_filename = "sof-cml-rt711-rt1308-mono-rt715.tplg",
DMakefile9 soc-acpi-intel-cml-match.o soc-acpi-intel-icl-match.o \
/linux-6.8/arch/x86/events/intel/
Dcstate.c49 * CNL,KBL,CML,TNT
54 * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
60 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML,
66 * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL,
72 * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL,
78 * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,
84 * KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL
88 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
93 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
98 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL,
/linux-6.8/Documentation/devicetree/bindings/clock/
Dti,lmk04832.yaml119 CML 16 mA 0x07
120 CML 24 mA 0x08
121 CML 32 mA 0x09
/linux-6.8/drivers/net/ethernet/microchip/sparx5/
Dsparx5_vcap_ag_api.h6 /* This file is autogenerated by cml-utils 2022-10-13 10:04:41 +0200.
/linux-6.8/drivers/net/ethernet/microchip/vcap/
Dvcap_model_kunit.h6 /* This file is autogenerated by cml-utils 2023-02-10 11:16:00 +0100.
Dvcap_ag_api.h6 /* This file is autogenerated by cml-utils 2023-03-13 10:16:42 +0100.
/linux-6.8/include/linux/platform_data/x86/
Dsoc.h38 SOC_INTEL_IS_CPU(cml, KABYLAKE_L);
/linux-6.8/drivers/gpu/drm/ci/
Dtest.yml224 i915:cml:
231 GPU_VERSION: cml
/linux-6.8/Documentation/devicetree/bindings/pci/
Dnvidia,tegra20-pcie.txt60 - cml (not required for Tegra20)
299 clock-names = "pex", "afi", "pll_e", "cml";
403 clock-names = "pex", "afi", "pll_e", "cml";
499 clock-names = "pex", "afi", "pll_e", "cml";
/linux-6.8/sound/soc/sof/intel/
Dpci-cnl.c112 [SOF_IPC_TYPE_3] = "sof-cml.ri",
/linux-6.8/drivers/phy/broadcom/
Dphy-bcm-ns-usb3.c85 /* Assert CML Divider ratio to 26 */ in bcm_ns_usb3_phy_init_ns_bx()
/linux-6.8/drivers/media/platform/st/sti/bdisp/
Dbdisp-reg.h41 u32 cml; member
/linux-6.8/drivers/mfd/
Dintel-lpss-pci.c237 /* CML-LP */
250 /* CML-H */
562 /* CML-V */
/linux-6.8/include/drm/
Di915_pciids.h448 /* CML GT1 */
460 /* CML GT2 */
/linux-6.8/drivers/thermal/intel/
Dintel_pch_thermal.c30 #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */
/linux-6.8/sound/soc/intel/boards/
DKconfig600 tristate "CML with RT1011 and RT5682 in I2S Mode"
/linux-6.8/drivers/net/ethernet/chelsio/cxgb/
Dvsc7326_reg.h109 #define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */
/linux-6.8/drivers/gpu/drm/i915/gt/uc/
Dintel_uc_fw.c105 fw_def(COMETLAKE, 5, guc_mmp(cml, 70, 1, 1)) \
126 fw_def(COMETLAKE, 5, huc_mmp(cml, 4, 0, 0)) \
/linux-6.8/drivers/clk/tegra/
Dclk-tegra30.c345 /* PLLE special case: use cpcon field to store cml divider value */
1259 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
/linux-6.8/drivers/gpu/drm/i915/gt/
Dintel_workarounds.c1102 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml in gen9_wa_init_mcr()
1135 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ in gen9_gt_workarounds_init()
2037 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml in cfl_whitelist_build()
/linux-6.8/drivers/gpu/drm/i915/display/
Dintel_modeset_setup.c925 /* Display WA #1142:kbl,cfl,cml */ in intel_early_display_was()
/linux-6.8/drivers/soundwire/
Dintel.c361 * (CNL/CML) or 38.4 MHz (ICL/TGL+). in intel_link_power_up()
/linux-6.8/drivers/pci/controller/
Dpci-tegra.c1213 dev_err(dev, "failed to enable CML clock: %d\n", err); in tegra_pcie_power_on()
1271 pcie->cml_clk = devm_clk_get(dev, "cml"); in tegra_pcie_clocks_get()

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