| /src/sys/contrib/device-tree/Bindings/bus/ |
| H A D | brcm,gisb-arb.yaml | 17 - brcm,bcm7445-gisb-arb # for other 28nm chips
21 - brcm,bcm74165-gisb-arb # for V7 new style 16nm chips
22 - brcm,bcm7278-gisb-arb # for V7 28nm chips
23 - brcm,bcm7435-gisb-arb # for newer 40nm chips
24 - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
25 - brcm,bcm7038-gisb-arb # for 130nm chips
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| H A D | brcm,gisb-arb.txt | 6 "brcm,bcm7278-gisb-arb" for V7 28nm chips
7 "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
8 "brcm,bcm7435-gisb-arb" for newer 40nm chips
9 "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
10 "brcm,bcm7038-gisb-arb" for 130nm chips
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| /src/share/man/man4/ |
| H A D | sym.4 | 7 .\" This driver also supports the following Symbios/LSI PCI SCSI chips:
105 only with newer chips.
115 also uses LOAD/STORE SCRIPTS instructions for chips that support it.
116 Only the early 810, 815 and 825 NCR chips do not support LOAD/STORE.
120 for chips that support LOAD/STORE.
126 For the early NCR 810, 815 and 825 chips, the driver uses a separate
128 This is because LOAD/STORE are not supported by these chips.
135 By default the driver only supports HVD for these chips.
136 For other chips that can support HVD but not LVD, the driver has to probe
144 885 chips, assuming Symbios Logic compatible implementation of HVD.
[all …]
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| H A D | dc.4 | 60 All of the clone chips
71 Some clone chips duplicate the 21143 fairly closely while others
80 Some chips (especially the PNIC) also have
87 These chips are used by many vendors which makes it
361 chips in normal operation, the driver must write a certain magic
385 driver programs 82c168 and 82c169 PNIC chips to use the store and
392 The 82c168 and 82c169 PNIC chips also have a receiver bug that
396 The chips appear to upload several kilobytes of garbage
404 The PNIC chips also sometimes generate a transmit underrun error when
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| H A D | vr.4 | 58 controller chips.
60 The VIA Rhine chips use bus master DMA and have a descriptor layout
63 chips.
65 layout is different however and the receive filter in the Rhine chips
70 The Rhine chips are meant to be interfaced with external
209 buffers prior to transmission in order to pacify the Rhine chips.
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| H A D | aibs.4 | 120 a combination of one or more physical hardware monitoring chips.
131 For example, voltage sensors in many hardware monitoring chips
158 Support for newer chips in
160 Newer chips may miss a native driver,
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| H A D | ucycom.4 | 55 chips.
56 These chips were designed to provide a low-cost transition path to USB
67 Cypress USB to RS232 bridge chips:
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| H A D | umcs.4 | 34 .Nd USB support for serial adapters based on the MCS7820 and MCS7840 chips
55 MCS7820 and MCS7840 chips.
58 Also, these chips
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| H A D | hptrr.4 | 51 set to 1 to permit driver attach to chips with generic Marvell (non-HighPoint)
53 These chips are also supported by
57 Some vendors are using same chips, but without providing RAID BIOS.
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| H A D | ath.4 | 57 These APIs are used by a wide variety of chips; most all chips with
78 Most chips also support an Atheros Turbo Mode (TM) that operates in
80 Some chips also support Turbo mode in the 2.4GHz range with 802.11g
88 All chips support WEP encryption.
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| /src/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | ccf.txt | 12 Example chips: T4240, B4860
15 Example chips: P5040, P5020, P4080, P3041, P2041
20 used for both CCF version 1 chips and CCF version 2
21 chips. It should be specified after either
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| /src/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | jedec,spi-nor.txt | 1 * SPI NOR flash: ST M25Pxx (and similar) serial flash chips
51 designate quirky versions of flash chips that do not support the
69 all chips and support for it can not be detected at runtime.
70 Refer to your chips' datasheet to check if this is supported
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| H A D | cypress,hyperflash.txt | 1 Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus
5 - compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips
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| /src/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-max3191x.txt | 17 Number of chips in the daisy-chain (default is 1).
21 (if all chips are wired to the same pin).
30 - maxim,modesel-8bit: Boolean whether the modesel pin of the chips is
39 (in 16-bit mode). Use this if the chips are powered
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| H A D | maxim,max31910.yaml | 31 description: Number of chips in the daisy-chain.
38 or 1 (if all chips are wired to the same pin).
57 Boolean whether the modesel pin of the chips is pulled high (8-bit mode).
68 the chips are powered through 5VOUT instead of VCC24V, in which case they
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| /src/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | microchip,mcp23s08.yaml | 14 chips.These chips provide 8 or 16 GPIO pins with either I2C or SPI interface.
51 Multiple SPI chips can share the same SPI chipselect. Set a bit in
57 chips.
65 have two IO banks IO 0-7 form bank 1 and IO 8-15 are bank 2. These chips
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| H A D | pinctrl-mcp23s08.txt | 28 multiple chips on the same chipselect. Have a look at
31 Required device specific properties (only for SPI chips):
34 chips - as the name suggests. Multiple SPI chips can share the same
40 least one bit to 1 for SPI chips.
58 IO 8-15 are bank 2. These chips have two different interrupt outputs:
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| /src/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | adi,ad7380.yaml | 99 chips.
104 chips.
109 chips.
114 chips.
164 # pseudo-differential chips require common mode voltage supplies,
165 # true differential chips don't use them
199 # All other chips from ad738x family use refio as optional external reference.
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| H A D | renesas,rcar-gyroadc.yaml | 80 thus for 8-channel operation, 8 chips are required.
82 of the TI/ADI chips to the GyroADC, while MISO line of each
88 8-channel operation, 8 chips are required.
90 of the MAX chips to the GyroADC, while MISO line of each Maxim
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| H A D | renesas,gyroadc.txt | 48 8 chips are required. A 3:8 chipselect demuxer is
49 required to connect the nCS line of the TI/ADI chips
57 8 chips are required. A 3:8 chipselect demuxer is
58 required to connect the nCS line of the MAX chips
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| /src/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | poseidon_reg_map_macro.h | 18 /* File: /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top/poseidon_reg_map_macro.h…
22 /* Path: /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top */
24 /* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint/ath_ansic.codegen*/
26 /* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top -I*/
27 /* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint -I */
28 /* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/env/blueprint -I*/
29 /* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig*/
31 /* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/top */
35 /* Sources: /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/rtl/rtc/blueprint/rtc_reg.rdl*/
36 /* /trees/kcwo/kcwo-dev/depot/chips/poseidon/1.0/blueprint/sysconfig/mac_pcu_reg_syscon…
[all …]
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| /src/sys/contrib/device-tree/Bindings/net/bluetooth/ |
| H A D | nxp,88w8987-bt.yaml | 7 title: NXP Bluetooth chips
10 This binding describes UART-attached NXP bluetooth chips. These chips
11 are dual-radio chips supporting WiFi and Bluetooth. The bluetooth
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| /src/sys/contrib/device-tree/Bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-channel.yaml | 11 CK, etc.) that connect one or more LPDDR chips to a host system. The main
13 amount of individual LPDDR chips and the ranks per chip.
32 chips, and the CA, CS, etc. pins of the different chips all shorted
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| /src/sys/contrib/device-tree/Bindings/tpm/ |
| H A D | tcg,tpm-tis-i2c.yaml | 24 Recent TPM 2.0 chips conform to this generic interface, others use a
30 - description: Generic TPM 2.0 chips conforming to TCG PTP interface
38 - description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface
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| /src/sys/contrib/device-tree/Bindings/pci/ |
| H A D | altr,pcie-root-port.yaml | 17 family of chips. The Stratix10 family of chips is supported by the
18 altr,pcie-root-port-2.0. The Agilex family of chips has three,
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